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(Updated Aug. 7, 2013, 6:39 a.m.) Review request for Default. Changes ------- Fixes a bug in addToReadQueue(). The bug showed up when the read packet is larger than DRAM burst size AND the first read burst hits in the write queue. Subsequent read bursts did not get the correct starting addr. Sorry, My bad Repository: gem5 Description ------- This patch gets rid of bytesPerCacheLine parameter and makes the DRAM configuration separate from cache line size. Instead of bytesPerCacheLine, I define a parameter for DRAM called burst_length. The burst_length parameter shows the length of a DRAM device burst in bits. Also, I replace lines_per_rowbuffer with device_rowbuffer_size to improve code portablity. Updates: - a burst length in beats for each memory type. - an interface width for each memory type. - the memory controller model is extended to reason about "system" packets vs "dram" packets and assemble the responses properly. It means that system packets larger than a full burst are split into multiple dram packets. Diffs (updated) ----- src/mem/SimpleDRAM.py UNKNOWN src/mem/simple_dram.hh UNKNOWN src/mem/simple_dram.cc UNKNOWN Diff: http://reviews.gem5.org/r/1927/diff/ Testing ------- Some short and fairly long tests on DDR3 and LPDRR3 with cache lines of 32, 64, and 128 bytes. Thanks, Amin Farmahini _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
