Sure will do. Sorry to keep iterating…I merely want to make sure nothing breaks.
Andreas From: Amin Farmahini <[email protected]<mailto:[email protected]>> Date: Wednesday, 24 July 2013 18:04 To: Andreas Hansson <[email protected]<mailto:[email protected]>> Cc: Default <[email protected]<mailto:[email protected]>> Subject: Re: Review Request 1927: mem: replacing bytesPerCacheLine with DRAM burstLength in SimpleDRAM I'll take a look at it on the weekend. I have not run any long tests, so chances are I messed up something. If you find any other things, please let me know. Thanks, Amin On Wed, Jul 24, 2013 at 9:40 AM, Andreas Hansson <[email protected]<mailto:[email protected]>> wrote: This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1927/ On July 24th, 2013, 2:29 p.m. UTC, Andreas Hansson wrote: src/mem/simple_dram.cc<http://reviews.gem5.org/r/1927/diff/4/?file=36780#file36780line366>(Diff revision 4) SimpleDRAM::decodeAddr(PacketPtr pkt) SimpleDRAM::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size) 353 addr = (addr | (burstSize - 1)) + 1; Perhaps a stupid question, but is this entirely safe? I guess it is...just thinking in terms of types, assumptions on powers of two etc. I ran the quick regressions and it seems at least the readPktSize stat changes significantly even with a DDR3 that has a 64 byte burst size. I haven't yet figured out why, but it would be good to understand better why the masking changes the stats. - Andreas On July 24th, 2013, 5:39 a.m. UTC, Amin Farmahini wrote: Review request for Default. By Amin Farmahini. Updated July 24, 2013, 5:39 a.m. Repository: gem5 Description This patch gets rid of bytesPerCacheLine parameter and makes the DRAM configuration separate from cache line size. Instead of bytesPerCacheLine, I define a parameter for DRAM called burst_length. The burst_length parameter shows the length of a DRAM device burst in bits. Also, I replace lines_per_rowbuffer with device_rowbuffer_size to improve code portablity. Updates: - a burst length in beats for each memory type. - an interface width for each memory type. - the memory controller model is extended to reason about "system" packets vs "dram" packets and assemble the responses properly. It means that system packets larger than a full burst are split into multiple dram packets. Testing None Diffs * src/mem/SimpleDRAM.py (UNKNOWN) * src/mem/simple_dram.hh (UNKNOWN) * src/mem/simple_dram.cc (UNKNOWN) View Diff<http://reviews.gem5.org/r/1927/diff/> -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
