changeset ebd7d3e04b5f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ebd7d3e04b5f
description:
x86: add tlb checkpointing
This patch adds checkpointing support to x86 tlb. It upgrades the
cpt_upgrader.py script so that previously created checkpoints can
be updated. It moves the checkpoint version to 6.
diffstat:
src/arch/x86/X86TLB.py | 2 +-
src/arch/x86/pagetable.cc | 15 ++-------------
src/arch/x86/tlb.cc | 31 +++++++++++++++++++++++++++++++
src/arch/x86/tlb.hh | 3 +--
src/sim/serialize.hh | 2 +-
util/cpt_upgrader.py | 15 +++++++++++++++
6 files changed, 51 insertions(+), 17 deletions(-)
diffs (150 lines):
diff -r 2492d7ccda7e -r ebd7d3e04b5f src/arch/x86/X86TLB.py
--- a/src/arch/x86/X86TLB.py Fri Jul 19 11:52:07 2013 +0200
+++ b/src/arch/x86/X86TLB.py Wed Aug 07 14:51:17 2013 -0500
@@ -54,6 +54,6 @@
type = 'X86TLB'
cxx_class = 'X86ISA::TLB'
cxx_header = 'arch/x86/tlb.hh'
- size = Param.Int(64, "TLB size")
+ size = Param.Unsigned(64, "TLB size")
walker = Param.X86PagetableWalker(\
X86PagetableWalker(), "page table walker")
diff -r 2492d7ccda7e -r ebd7d3e04b5f src/arch/x86/pagetable.cc
--- a/src/arch/x86/pagetable.cc Fri Jul 19 11:52:07 2013 +0200
+++ b/src/arch/x86/pagetable.cc Wed Aug 07 14:51:17 2013 -0500
@@ -70,25 +70,14 @@
{
UNSERIALIZE_SCALAR(paddr);
UNSERIALIZE_SCALAR(vaddr);
- //
- // The logBytes scalar variable replaced the previous size variable.
- // The following code maintains backwards compatibility with previous
- // checkpoints using the old size variable.
- //
- if (UNSERIALIZE_OPT_SCALAR(logBytes) == false) {
- int size;
- UNSERIALIZE_SCALAR(size);
- logBytes = log2(size);
- }
+ UNSERIALIZE_SCALAR(logBytes);
UNSERIALIZE_SCALAR(writable);
UNSERIALIZE_SCALAR(user);
UNSERIALIZE_SCALAR(uncacheable);
UNSERIALIZE_SCALAR(global);
UNSERIALIZE_SCALAR(patBit);
UNSERIALIZE_SCALAR(noExec);
- if (UNSERIALIZE_OPT_SCALAR(lruSeq) == false) {
- lruSeq = 0;
- }
+ UNSERIALIZE_SCALAR(lruSeq);
}
}
diff -r 2492d7ccda7e -r ebd7d3e04b5f src/arch/x86/tlb.cc
--- a/src/arch/x86/tlb.cc Fri Jul 19 11:52:07 2013 +0200
+++ b/src/arch/x86/tlb.cc Wed Aug 07 14:51:17 2013 -0500
@@ -439,11 +439,42 @@
void
TLB::serialize(std::ostream &os)
{
+ // Only store the entries in use.
+ uint32_t _size = size - freeList.size();
+ SERIALIZE_SCALAR(_size);
+ SERIALIZE_SCALAR(lruSeq);
+
+ uint32_t _count = 0;
+
+ for (uint32_t x = 0; x < size; x++) {
+ if (tlb[x].trieHandle != NULL) {
+ os << "\n[" << csprintf("%s.Entry%d", name(), _count) << "]\n";
+ tlb[x].serialize(os);
+ _count++;
+ }
+ }
}
void
TLB::unserialize(Checkpoint *cp, const std::string §ion)
{
+ // Do not allow to restore with a smaller tlb.
+ uint32_t _size;
+ UNSERIALIZE_SCALAR(_size);
+ if (_size > size) {
+ fatal("TLB size less than the one in checkpoint!");
+ }
+
+ UNSERIALIZE_SCALAR(lruSeq);
+
+ for (uint32_t x = 0; x < _size; x++) {
+ TlbEntry *newEntry = freeList.front();
+ freeList.pop_front();
+
+ newEntry->unserialize(cp, csprintf("%s.Entry%d", name(), x));
+ newEntry->trieHandle = trie.insert(newEntry->vaddr,
+ TlbEntryTrie::MaxBits - newEntry->logBytes, newEntry);
+ }
}
BaseMasterPort *
diff -r 2492d7ccda7e -r ebd7d3e04b5f src/arch/x86/tlb.hh
--- a/src/arch/x86/tlb.hh Fri Jul 19 11:52:07 2013 +0200
+++ b/src/arch/x86/tlb.hh Wed Aug 07 14:51:17 2013 -0500
@@ -95,12 +95,11 @@
void demapPage(Addr va, uint64_t asn);
protected:
- int size;
+ uint32_t size;
TlbEntry * tlb;
EntryList freeList;
- EntryList entryList;
TlbEntryTrie trie;
uint64_t lruSeq;
diff -r 2492d7ccda7e -r ebd7d3e04b5f src/sim/serialize.hh
--- a/src/sim/serialize.hh Fri Jul 19 11:52:07 2013 +0200
+++ b/src/sim/serialize.hh Wed Aug 07 14:51:17 2013 -0500
@@ -57,7 +57,7 @@
* SimObject shouldn't cause the version number to increase, only changes to
* existing objects such as serializing/unserializing more state, changing
sizes
* of serialized arrays, etc. */
-static const uint64_t gem5CheckpointVersion = 0x0000000000000005;
+static const uint64_t gem5CheckpointVersion = 0x0000000000000006;
template <class T>
void paramOut(std::ostream &os, const std::string &name, const T ¶m);
diff -r 2492d7ccda7e -r ebd7d3e04b5f util/cpt_upgrader.py
--- a/util/cpt_upgrader.py Fri Jul 19 11:52:07 2013 +0200
+++ b/util/cpt_upgrader.py Wed Aug 07 14:51:17 2013 -0500
@@ -193,7 +193,21 @@
del mr[137]
cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr))
+# Version 6 of the checkpoint format adds tlb to x86 checkpoints
+def from_5(cpt):
+ if cpt.get('root','isa') == 'x86':
+ for sec in cpt.sections():
+ import re
+ # Search for all ISA sections
+ if re.search('.*sys.*\.cpu.*\.dtb$', sec):
+ cpt.set(sec, '_size', '0')
+ cpt.set(sec, 'lruSeq', '0')
+ if re.search('.*sys.*\.cpu.*\.itb$', sec):
+ cpt.set(sec, '_size', '0')
+ cpt.set(sec, 'lruSeq', '0')
+ else:
+ print "ISA is not x86"
migrations = []
migrations.append(from_0)
@@ -201,6 +215,7 @@
migrations.append(from_2)
migrations.append(from_3)
migrations.append(from_4)
+migrations.append(from_5)
verbose_print = False
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