changeset 168e94599c2a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=168e94599c2a
description:
alpha: Check interrupts before quiesce
This patch adds a check to the quiesce operation to ensure that the
CPU does not suspend itself when there are unmasked interrupts
pending. Without this patch there are corner cases when the CPU gets
an interrupt before the quiesce is executed and then never wakes up
again.
diffstat:
src/arch/alpha/isa/decoder.isa | 21 ++++++++++++++++++++-
1 files changed, 20 insertions(+), 1 deletions(-)
diffs (37 lines):
diff -r 4807b780ed0a -r 168e94599c2a src/arch/alpha/isa/decoder.isa
--- a/src/arch/alpha/isa/decoder.isa Mon Aug 19 03:52:29 2013 -0400
+++ b/src/arch/alpha/isa/decoder.isa Mon Aug 19 03:52:29 2013 -0400
@@ -1,5 +1,17 @@
// -*- mode:c++ -*-
+// Copyright (c) 2013 ARM Limited
+// All rights reserved
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder. You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
// Copyright (c) 2003-2006 The Regents of The University of Michigan
// All rights reserved.
//
@@ -929,7 +941,14 @@
PseudoInst::arm(xc->tcBase());
}}, IsNonSpeculative);
0x01: quiesce({{
- PseudoInst::quiesce(xc->tcBase());
+ // Don't sleep if (unmasked) interrupts are pending
+ Interrupts* interrupts =
+ xc->tcBase()->getCpuPtr()->getInterruptController();
+ if (interrupts->checkInterrupts(xc->tcBase())) {
+ PseudoInst::quiesceSkip(xc->tcBase());
+ } else {
+ PseudoInst::quiesce(xc->tcBase());
+ }
}}, IsNonSpeculative, IsQuiesce);
0x02: quiesceNs({{
PseudoInst::quiesceNs(xc->tcBase(), R16);
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