changeset f47274776aa0 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f47274776aa0
description:
power: Add voltage domains to the clock domains
This patch adds the notion of voltage domains, and groups clock
domains that operate under the same voltage (i.e. power supply) into
domains. Each clock domain is required to be associated with a voltage
domain, and the latter requires the voltage to be explicitly set.
A voltage domain is an independently controllable voltage supply being
provided to section of the design. Thus, if you wish to perform
dynamic voltage scaling on a CPU, its clock domain should be
associated with a separate voltage domain.
The current implementation of the voltage domain does not take into
consideration cases where there are derived voltage domains running at
ratio of native voltage domains, as with the case where there can be
on-chip buck/boost (charge pumps) voltage regulation logic.
The regression and configuration scripts are updated with a generic
voltage domain for the system, and one for the CPUs.
diffstat:
configs/common/Options.py | 4 +
configs/example/fs.py | 23 ++++++-
configs/example/se.py | 15 ++++-
src/python/m5/params.py | 19 +++++-
src/python/m5/util/convert.py | 12 +++
src/sim/ClockDomain.py | 4 +
src/sim/SConscript | 3 +
src/sim/VoltageDomain.py | 47 +++++++++++++++
src/sim/clock_domain.cc | 12 +++-
src/sim/clock_domain.hh | 29 ++++++++-
src/sim/voltage_domain.cc | 68 +++++++++++++++++++++
src/sim/voltage_domain.hh | 84 +++++++++++++++++++++++++++
tests/configs/base_config.py | 9 ++-
tests/configs/memtest-ruby.py | 13 ++-
tests/configs/memtest.py | 10 ++-
tests/configs/pc-simple-timing-ruby.py | 11 ++-
tests/configs/rubytest-ruby.py | 10 ++-
tests/configs/simple-timing-ruby.py | 13 ++-
tests/configs/t1000-simple-atomic.py | 7 +-
tests/configs/tgen-simple-dram.py | 4 +-
tests/configs/tgen-simple-mem.py | 4 +-
tests/configs/twosys-tsunami-simple-atomic.py | 28 +++++++-
22 files changed, 390 insertions(+), 39 deletions(-)
diffs (truncated from 768 to 300 lines):
diff -r 014ff1fbff6d -r f47274776aa0 configs/common/Options.py
--- a/configs/common/Options.py Mon Aug 19 03:52:27 2013 -0400
+++ b/configs/common/Options.py Mon Aug 19 03:52:28 2013 -0400
@@ -64,6 +64,10 @@
help = "type of cpu to run with")
parser.add_option("--checker", action="store_true");
parser.add_option("-n", "--num-cpus", type="int", default=1)
+ parser.add_option("--sys-voltage", action="store", type="string",
+ default='1.0V',
+ help = """Top-level voltage for blocks running at system
+ power supply""")
parser.add_option("--sys-clock", action="store", type="string",
default='1GHz',
help = """Top-level clock for blocks running at system
diff -r 014ff1fbff6d -r f47274776aa0 configs/example/fs.py
--- a/configs/example/fs.py Mon Aug 19 03:52:27 2013 -0400
+++ b/configs/example/fs.py Mon Aug 19 03:52:28 2013 -0400
@@ -116,11 +116,20 @@
else:
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
+# Create a top-level voltage domain
+test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
+
# Create a source clock for the system and set the clock period
-test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock)
+test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
+ voltage_domain = test_sys.voltage_domain)
+
+# Create a CPU voltage domain
+test_sys.cpu_voltage_domain = VoltageDomain()
# Create a source clock for the CPUs and set the clock period
-test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)
+test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
+ voltage_domain =
+ test_sys.cpu_voltage_domain)
if options.kernel is not None:
test_sys.kernel = binary(options.kernel)
@@ -182,11 +191,19 @@
elif buildEnv['TARGET_ISA'] == 'arm':
drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
+ # Create a top-level voltage domain
+ drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
+
# Create a source clock for the system and set the clock period
drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock)
+ # Create a CPU voltage domain
+ drive_sys.cpu_voltage_domain = VoltageDomain()
+
# Create a source clock for the CPUs and set the clock period
- drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)
+ drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
+ voltage_domain =
+ drive_sys.cpu_voltage_domain)
drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
cpu_id=0)
diff -r 014ff1fbff6d -r f47274776aa0 configs/example/se.py
--- a/configs/example/se.py Mon Aug 19 03:52:27 2013 -0400
+++ b/configs/example/se.py Mon Aug 19 03:52:28 2013 -0400
@@ -159,11 +159,22 @@
system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
physmem = MemClass(range=AddrRange(options.mem_size)),
mem_mode = test_mem_mode,
- clk_domain = SrcClockDomain(clock = options.sys_clock),
cache_line_size = options.cacheline_size)
+# Create a top-level voltage domain
+system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
+
+# Create a source clock for the system and set the clock period
+system.clk_domain = SrcClockDomain(clock = options.sys_clock,
+ voltage_domain = system.voltage_domain)
+
+# Create a CPU voltage domain
+system.cpu_voltage_domain = VoltageDomain()
+
# Create a separate clock domain for the CPUs
-system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)
+system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
+ voltage_domain =
+ system.cpu_voltage_domain)
# All cpus belong to a common cpu_clk_domain, therefore running at a common
# frequency.
diff -r 014ff1fbff6d -r f47274776aa0 src/python/m5/params.py
--- a/src/python/m5/params.py Mon Aug 19 03:52:27 2013 -0400
+++ b/src/python/m5/params.py Mon Aug 19 03:52:28 2013 -0400
@@ -1250,6 +1250,23 @@
def ini_str(self):
return self.period.ini_str()
+class Voltage(float,ParamValue):
+ cxx_type = 'double'
+ def __new__(cls, value):
+ # convert to voltage
+ val = convert.toVoltage(value)
+ return super(cls, Voltage).__new__(cls, val)
+
+ def __str__(self):
+ return str(self.val)
+
+ def getValue(self):
+ value = float(self)
+ return value
+
+ def ini_str(self):
+ return '%f' % self.getValue()
+
class NetworkBandwidth(float,ParamValue):
cxx_type = 'float'
def __new__(cls, value):
@@ -1637,7 +1654,7 @@
'TcpPort', 'UdpPort', 'EthernetAddr',
'IpAddress', 'IpNetmask', 'IpWithPort',
'MemorySize', 'MemorySize32',
- 'Latency', 'Frequency', 'Clock',
+ 'Latency', 'Frequency', 'Clock', 'Voltage',
'NetworkBandwidth', 'MemoryBandwidth',
'AddrRange',
'MaxAddr', 'MaxTick', 'AllMemory',
diff -r 014ff1fbff6d -r f47274776aa0 src/python/m5/util/convert.py
--- a/src/python/m5/util/convert.py Mon Aug 19 03:52:27 2013 -0400
+++ b/src/python/m5/util/convert.py Mon Aug 19 03:52:28 2013 -0400
@@ -299,3 +299,15 @@
if not 0 <= int(port) <= 0xffff:
raise ValueError, 'invalid port %s' % port
return (ip, int(port))
+
+def toVoltage(value):
+ if not isinstance(value, str):
+ raise TypeError, "wrong type '%s' should be str" % type(value)
+
+ if value.endswith('mV'):
+ return float(value[:-2]) * milli
+ elif value.endswith('V'):
+ return float(value[:-1])
+
+ raise ValueError, "cannot convert '%s' to voltage" % value
+
diff -r 014ff1fbff6d -r f47274776aa0 src/sim/ClockDomain.py
--- a/src/sim/ClockDomain.py Mon Aug 19 03:52:27 2013 -0400
+++ b/src/sim/ClockDomain.py Mon Aug 19 03:52:28 2013 -0400
@@ -38,6 +38,7 @@
from m5.params import *
from m5.SimObject import SimObject
+from m5.proxy import *
# Abstract clock domain
class ClockDomain(SimObject):
@@ -51,6 +52,9 @@
cxx_header = "sim/clock_domain.hh"
clock = Param.Clock("Clock period")
+ # A source clock must be associated with a voltage domain
+ voltage_domain = Param.VoltageDomain("Voltage domain")
+
# Derived clock domain with a parent clock domain and a frequency
# divider
class DerivedClockDomain(ClockDomain):
diff -r 014ff1fbff6d -r f47274776aa0 src/sim/SConscript
--- a/src/sim/SConscript Mon Aug 19 03:52:27 2013 -0400
+++ b/src/sim/SConscript Mon Aug 19 03:52:28 2013 -0400
@@ -35,6 +35,7 @@
SimObject('Root.py')
SimObject('InstTracer.py')
SimObject('ClockDomain.py')
+SimObject('VoltageDomain.py')
Source('arguments.cc')
Source('async.cc')
@@ -52,6 +53,7 @@
Source('stat_control.cc')
Source('syscall_emul.cc')
Source('clock_domain.cc')
+Source('voltage_domain.cc')
if env['TARGET_ISA'] != 'no':
SimObject('Process.py')
@@ -84,3 +86,4 @@
DebugFlag('VtoPhys')
DebugFlag('WorkItems')
DebugFlag('ClockDomain')
+DebugFlag('VoltageDomain')
diff -r 014ff1fbff6d -r f47274776aa0 src/sim/VoltageDomain.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/sim/VoltageDomain.py Mon Aug 19 03:52:28 2013 -0400
@@ -0,0 +1,47 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Vasileios Spiliopoulos
+# Akash Bagdia
+
+from m5.SimObject import SimObject
+from m5.params import *
+
+class VoltageDomain(SimObject):
+ type = 'VoltageDomain'
+ cxx_header = "sim/voltage_domain.hh"
+ # We use a default voltage of 1V to avoid forcing users to set it
+ # even if they are not interested in using the functionality
+ voltage = Param.Voltage('1V', "Operational voltage")
diff -r 014ff1fbff6d -r f47274776aa0 src/sim/clock_domain.cc
--- a/src/sim/clock_domain.cc Mon Aug 19 03:52:27 2013 -0400
+++ b/src/sim/clock_domain.cc Mon Aug 19 03:52:28 2013 -0400
@@ -44,8 +44,16 @@
#include "params/DerivedClockDomain.hh"
#include "params/SrcClockDomain.hh"
#include "sim/clock_domain.hh"
+#include "sim/voltage_domain.hh"
-SrcClockDomain::SrcClockDomain(const Params *p) : ClockDomain(p)
+double
+ClockDomain::voltage() const
+{
+ return _voltageDomain->voltage();
+}
+
+SrcClockDomain::SrcClockDomain(const Params *p) :
+ ClockDomain(p, p->voltage_domain)
{
clockPeriod(p->clock);
}
@@ -76,7 +84,7 @@
}
DerivedClockDomain::DerivedClockDomain(const Params *p) :
- ClockDomain(p),
+ ClockDomain(p, p->clk_domain->voltageDomain()),
parent(*p->clk_domain),
clockDivider(p->clk_divider)
{
diff -r 014ff1fbff6d -r f47274776aa0 src/sim/clock_domain.hh
--- a/src/sim/clock_domain.hh Mon Aug 19 03:52:27 2013 -0400
+++ b/src/sim/clock_domain.hh Mon Aug 19 03:52:28 2013 -0400
@@ -56,10 +56,12 @@
* Forward declaration
*/
class DerivedClockDomain;
+class VoltageDomain;
/**
* The ClockDomain provides clock to group of clocked objects bundled
- * under the same clock domain. The clock domains provide support for
+ * under the same clock domain. The clock domains, in turn, are
+ * grouped into voltage domains. The clock domains provide support for
* a hierarchial structure with source and derived domains.
*/
class ClockDomain : public SimObject
@@ -74,6 +76,11 @@
Tick _clockPeriod;
/**
+ * Voltage domain this clock domain belongs to
+ */
+ VoltageDomain *_voltageDomain;
+
+ /**
* Pointers to potential derived clock domains so we can propagate
* changes.
*/
@@ -82,7 +89,10 @@
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
