[gem5-dev] changeset in gem5: cpu: Fix timing CPU drain check

[Andreas Hansson]

changeset 5995f4d33a11 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=5995f4d33a11
description:
        cpu: Fix timing CPU drain check

        This patch modifies the SimpleTimingCPU drain check to also consider
        the fetch event. Previously, there was an assumption that there is
        never a fetch event scheduled if the CPU is not executing
        microcode. However, when a context is activated, a fetch even is
        scheduled, and microPC() is zero.

diffstat:

 src/cpu/simple/timing.cc |  1 -
 src/cpu/simple/timing.hh |  7 +++++--
 2 files changed, 5 insertions(+), 3 deletions(-)

diffs (31 lines):

diff -r 168e94599c2a -r 5995f4d33a11 src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc  Mon Aug 19 03:52:29 2013 -0400
+++ b/src/cpu/simple/timing.cc  Mon Aug 19 03:52:30 2013 -0400
@@ -109,7 +109,6 @@
 
     if (_status == Idle ||
         (_status == BaseSimpleCPU::Running && isDrained())) {
-        assert(!fetchEvent.scheduled());
         DPRINTF(Drain, "No need to drain.\n");
         return 0;
     } else {
diff -r 168e94599c2a -r 5995f4d33a11 src/cpu/simple/timing.hh
--- a/src/cpu/simple/timing.hh  Mon Aug 19 03:52:29 2013 -0400
+++ b/src/cpu/simple/timing.hh  Mon Aug 19 03:52:30 2013 -0400
@@ -320,11 +320,14 @@
      *     of a gem5 microcode sequence.
      *
      * <li>Stay at PC is true.
+     *
+     * <li>A fetch event is scheduled. Normally this would never be the
+           case with microPC() == 0, but right after a context is
+           activated it can happen.
      * </ul>
      */
     bool isDrained() {
-        return microPC() == 0 &&
-            !stayAtPC;
+        return microPC() == 0 && !stayAtPC && !fetchEvent.scheduled();
     }
 
     /**
_______________________________________________
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev