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Ship it! Ship It! - Andreas Hansson On Aug. 27, 2013, 1:27 a.m., Steve Reinhardt wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1981/ > ----------------------------------------------------------- > > (Updated Aug. 27, 2013, 1:27 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 9846:76e56335fbfe > --------------------------- > cpu: clean up architectural register classification > > Move from a poorly documented scheme where the mapping > of unified architectural register indices to register > classes is hardcoded all over to one where there's an > enum for the register classes and a function that > encapsulates the mapping. > > > Diffs > ----- > > src/arch/arm/insts/misc.cc 3f6e2f267aba6571c478fcd83c4a1b9d6564084f > src/arch/arm/insts/static_inst.cc 3f6e2f267aba6571c478fcd83c4a1b9d6564084f > src/arch/power/insts/static_inst.cc > 3f6e2f267aba6571c478fcd83c4a1b9d6564084f > src/arch/x86/insts/static_inst.cc 3f6e2f267aba6571c478fcd83c4a1b9d6564084f > src/cpu/SConscript 3f6e2f267aba6571c478fcd83c4a1b9d6564084f > src/cpu/checker/cpu_impl.hh 3f6e2f267aba6571c478fcd83c4a1b9d6564084f > src/cpu/inorder/cpu.hh 3f6e2f267aba6571c478fcd83c4a1b9d6564084f > src/cpu/inorder/cpu.cc 3f6e2f267aba6571c478fcd83c4a1b9d6564084f > src/cpu/inorder/inorder_dyn_inst.cc > 3f6e2f267aba6571c478fcd83c4a1b9d6564084f > src/cpu/o3/dyn_inst.hh 3f6e2f267aba6571c478fcd83c4a1b9d6564084f > src/cpu/o3/rename_impl.hh 3f6e2f267aba6571c478fcd83c4a1b9d6564084f > src/cpu/reg_class.hh PRE-CREATION > src/cpu/reg_class.cc PRE-CREATION > > Diff: http://reviews.gem5.org/r/1981/diff/ > > > Testing > ------- > > > Thanks, > > Steve Reinhardt > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
