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Ship it! src/cpu/o3/O3CPU.py <http://reviews.gem5.org/r/1989/#comment4415> Does this mean that each int reg has a cc reg attached to it? - Nilay Vaish On Aug. 22, 2013, 12:41 a.m., Steve Reinhardt wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1989/ > ----------------------------------------------------------- > > (Updated Aug. 22, 2013, 12:41 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 9852:5eb1f617fea1 > --------------------------- > arch/x86: add support for explicit CC register file > > Convert condition code registers from being specialized > ("pseudo") integer registers to using the recently > added CC register class. > > Nilay Vaish also contributed to this patch. > > > Diffs > ----- > > src/arch/x86/isa/operands.isa 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/arch/x86/registers.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/arch/x86/regs/ccr.hh PRE-CREATION > src/arch/x86/regs/int.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/arch/x86/utility.cc 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/arch/x86/x86_traits.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/o3/O3CPU.py 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > > Diff: http://reviews.gem5.org/r/1989/diff/ > > > Testing > ------- > > > Thanks, > > Steve Reinhardt > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
