> On Aug. 27, 2013, 8:48 a.m., Nilay Vaish wrote: > > src/cpu/o3/O3CPU.py, line 121 > > <http://reviews.gem5.org/r/1989/diff/1/?file=37311#file37311line121> > > > > Does this mean that each int reg has a cc reg attached to it?
Yes, the intent here is to have a performance model that's equivalent to every int reg having an associated set of flags, without the major surgery that would be required to have the O3 model actually implement that. Really all that matters is that the number of physical integer registers is the only constraint on renaming, and you never have to stall because you ran out of physical CC regs while there were still physical int regs available. To answer your question on the other review, I don't know of any commercial processors that explicitly rename CC regs as a separate resource, but I haven't kept up with all the details (e.g., some of the high-end SPARCs from Fujitsu might conceivably do this). I think this code would support that model as well, if anyone wanted to test it out. - Steve ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1989/#review4652 ----------------------------------------------------------- On Aug. 21, 2013, 5:41 p.m., Steve Reinhardt wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1989/ > ----------------------------------------------------------- > > (Updated Aug. 21, 2013, 5:41 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 9852:5eb1f617fea1 > --------------------------- > arch/x86: add support for explicit CC register file > > Convert condition code registers from being specialized > ("pseudo") integer registers to using the recently > added CC register class. > > Nilay Vaish also contributed to this patch. > > > Diffs > ----- > > src/arch/x86/isa/operands.isa 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/arch/x86/registers.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/arch/x86/regs/ccr.hh PRE-CREATION > src/arch/x86/regs/int.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/arch/x86/utility.cc 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/arch/x86/x86_traits.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/o3/O3CPU.py 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > > Diff: http://reviews.gem5.org/r/1989/diff/ > > > Testing > ------- > > > Thanks, > > Steve Reinhardt > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
