changeset 676d3dcf1cc2 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=676d3dcf1cc2
description:
mem: Use a flag instead of address bit 63 for generic IPRs
Using address bit 63 to identify generic IPRs caused problems on
SPARC, where IPRs are heavily used. This changeset redefines how
generic IPRs are identified. Instead of using bit 63, we now use a
separate flag (GENERIC_IPR) a memory request.
diffstat:
src/arch/generic/mmapped_ipr.cc | 4 ++--
src/arch/generic/mmapped_ipr.hh | 21 ++++++---------------
src/arch/x86/tlb.cc | 2 +-
src/mem/request.hh | 4 ++++
4 files changed, 13 insertions(+), 18 deletions(-)
diffs (96 lines):
diff -r 5101c7044d32 -r 676d3dcf1cc2 src/arch/generic/mmapped_ipr.cc
--- a/src/arch/generic/mmapped_ipr.cc Mon Oct 14 13:58:02 2013 -0500
+++ b/src/arch/generic/mmapped_ipr.cc Tue Oct 15 13:24:35 2013 +0200
@@ -53,7 +53,7 @@
GenericISA::handleGenericIprRead(ThreadContext *xc, Packet *pkt)
{
Addr va(pkt->getAddr());
- Addr cls((va & IPR_CLASS_MASK) >> IPR_CLASS_SHIFT);
+ Addr cls(va >> IPR_CLASS_SHIFT);
switch (cls) {
case IPR_CLASS_PSEUDO_INST:
@@ -70,7 +70,7 @@
GenericISA::handleGenericIprWrite(ThreadContext *xc, Packet *pkt)
{
Addr va(pkt->getAddr());
- Addr cls((va & IPR_CLASS_MASK) >> IPR_CLASS_SHIFT);
+ Addr cls(va >> IPR_CLASS_SHIFT);
switch (cls) {
case IPR_CLASS_PSEUDO_INST:
diff -r 5101c7044d32 -r 676d3dcf1cc2 src/arch/generic/mmapped_ipr.hh
--- a/src/arch/generic/mmapped_ipr.hh Mon Oct 14 13:58:02 2013 -0500
+++ b/src/arch/generic/mmapped_ipr.hh Tue Oct 15 13:24:35 2013 +0200
@@ -49,23 +49,12 @@
* Memory requests with the MMAPPED_IPR flag are generally mapped
* to registers. There is a class of these registers that are
* internal to gem5, for example gem5 pseudo-ops in virtualized
- * mode.
- *
- * In order to make the IPR space manageable we always set bit 63
- * (IPR_GENERIC) for accesses that should be handled by the
- * generic ISA code. Architectures may use the rest of the IPR
- * space internally.
+ * mode. Such IPRs always have the flag GENERIC_IPR set and are
+ * handled by this code.
*/
- /** Is this a generic IPR access? */
- const Addr IPR_GENERIC = ULL(0x8000000000000000);
-
- /** @{ */
- /** Mask when extracting the class of a generic IPR */
- const Addr IPR_CLASS_MASK = ULL(0x7FFF000000000000);
/** Shift amount when extracting the class of a generic IPR */
const int IPR_CLASS_SHIFT = 48;
- /** @} */
/** Mask to extract the offset in within a generic IPR class */
const Addr IPR_IN_CLASS_MASK = ULL(0x0000FFFFFFFFFFFF);
@@ -94,7 +83,7 @@
inline Addr
iprAddressPseudoInst(uint8_t func, uint8_t subfunc)
{
- return IPR_GENERIC | (IPR_CLASS_PSEUDO_INST << IPR_CLASS_SHIFT) |
+ return (IPR_CLASS_PSEUDO_INST << IPR_CLASS_SHIFT) |
(func << 8) | subfunc;
}
@@ -113,7 +102,9 @@
inline bool
isGenericIprAccess(const Packet *pkt)
{
- return pkt->getAddr() & IPR_GENERIC;
+ Request::Flags flags(pkt->req->getFlags());
+ return (flags & Request::MMAPPED_IPR) &&
+ (flags & Request::GENERIC_IPR);
}
/**
diff -r 5101c7044d32 -r 676d3dcf1cc2 src/arch/x86/tlb.cc
--- a/src/arch/x86/tlb.cc Mon Oct 14 13:58:02 2013 -0500
+++ b/src/arch/x86/tlb.cc Tue Oct 15 13:24:35 2013 +0200
@@ -257,7 +257,7 @@
req->setPaddr(x86LocalAPICAddress(tc->contextId(),
paddr - apicRange.start()));
} else if (m5opRange.contains(paddr)) {
- req->setFlags(Request::MMAPPED_IPR);
+ req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR);
req->setPaddr(GenericISA::iprAddressPseudoInst(
(paddr >> 8) & 0xFF,
paddr & 0xFF));
diff -r 5101c7044d32 -r 676d3dcf1cc2 src/mem/request.hh
--- a/src/mem/request.hh Mon Oct 14 13:58:02 2013 -0500
+++ b/src/mem/request.hh Tue Oct 15 13:24:35 2013 +0200
@@ -127,6 +127,10 @@
/** The request should be marked as LRU. */
static const FlagsType EVICT_NEXT = 0x04000000;
+ /** The request should be handled by the generic IPR code (only
+ * valid together with MMAPPED_IPR) */
+ static const FlagsType GENERIC_IPR = 0x08000000;
+
/** These flags are *not* cleared when a Request object is reused
(assigned a new address). */
static const FlagsType STICKY_FLAGS = INST_FETCH;
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