changeset 3de4393f5649 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3de4393f5649
description:
mem: Rename the ASI_BITS flag field in Request
ASI_BITS in the Request object were originally used to store a memory
request's ASI on SPARC. This is not the case any more since other ISAs
use the ASI bits to store architecture-dependent information. This
changeset renames the ASI_BITS to ARCH_BITS which better describes
their use. Additionally, the getAsi() accessor is renamed to
getArchFlags().
diffstat:
src/arch/sparc/tlb.cc | 12 ++++++------
src/mem/request.hh | 28 +++++++++++++++++++++-------
2 files changed, 27 insertions(+), 13 deletions(-)
diffs (108 lines):
diff -r 676d3dcf1cc2 -r 3de4393f5649 src/arch/sparc/tlb.cc
--- a/src/arch/sparc/tlb.cc Tue Oct 15 13:24:35 2013 +0200
+++ b/src/arch/sparc/tlb.cc Tue Oct 15 13:26:34 2013 +0200
@@ -420,7 +420,7 @@
Addr vaddr = req->getVaddr();
TlbEntry *e;
- assert(req->getAsi() == ASI_IMPLICIT);
+ assert(req->getArchFlags() == ASI_IMPLICIT);
DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
vaddr, req->getSize());
@@ -536,7 +536,7 @@
Addr vaddr = req->getVaddr();
Addr size = req->getSize();
ASI asi;
- asi = (ASI)req->getAsi();
+ asi = (ASI)req->getArchFlags();
bool implicit = false;
bool hpriv = bits(tlbdata,0,0);
bool unaligned = vaddr & (size - 1);
@@ -858,11 +858,11 @@
TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
{
Addr va = pkt->getAddr();
- ASI asi = (ASI)pkt->req->getAsi();
+ ASI asi = (ASI)pkt->req->getArchFlags();
uint64_t temp;
DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
- (uint32_t)pkt->req->getAsi(), pkt->getAddr());
+ (uint32_t)pkt->req->getArchFlags(), pkt->getAddr());
TLB *itb = tc->getITBPtr();
@@ -1044,7 +1044,7 @@
{
uint64_t data = pkt->get<uint64_t>();
Addr va = pkt->getAddr();
- ASI asi = (ASI)pkt->req->getAsi();
+ ASI asi = (ASI)pkt->req->getArchFlags();
Addr ta_insert;
Addr va_insert;
@@ -1286,7 +1286,7 @@
default:
doMmuWriteError:
panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
- (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
+ (uint32_t)pkt->req->getArchFlags(), pkt->getAddr(), data);
}
pkt->makeAtomicResponse();
return Cycles(1);
diff -r 676d3dcf1cc2 -r 3de4393f5649 src/mem/request.hh
--- a/src/mem/request.hh Tue Oct 15 13:24:35 2013 +0200
+++ b/src/mem/request.hh Tue Oct 15 13:26:34 2013 +0200
@@ -86,10 +86,17 @@
{
public:
typedef uint32_t FlagsType;
+ typedef uint8_t ArchFlagsType;
typedef ::Flags<FlagsType> Flags;
- /** ASI information for this request if it exists. */
- static const FlagsType ASI_BITS = 0x000000FF;
+ /**
+ * Architecture specific flags.
+ *
+ * These bits int the flag field are reserved for
+ * architecture-specific code. For example, SPARC uses them to
+ * represent ASIs.
+ */
+ static const FlagsType ARCH_BITS = 0x000000FF;
/** The request was an instruction fetch. */
static const FlagsType INST_FETCH = 0x00000100;
/** The virtual address is also the physical address. */
@@ -422,6 +429,13 @@
_flags.set(flags);
}
+ void
+ setArchFlags(Flags flags)
+ {
+ assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
+ _flags.set(flags & ARCH_BITS);
+ }
+
/** Accessor function for vaddr.*/
Addr
getVaddr()
@@ -452,12 +466,12 @@
_asid = asid;
}
- /** Accessor function for asi.*/
- uint8_t
- getAsi()
+ /** Accessor function for architecture-specific flags.*/
+ ArchFlagsType
+ getArchFlags()
{
- assert(privateFlags.isSet(VALID_VADDR));
- return _flags & ASI_BITS;
+ assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
+ return _flags & ARCH_BITS;
}
/** Accessor function to check if sc result is valid. */
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