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Review request for Default. Repository: gem5 Description ------- Changeset 9914:0ebbd47c9444 --------------------------- mem: Add tRAS parameter to the DRAM controller model This patch adds an explicit tRAS parameter to the DRAM controller model. Previously tRAS was, rather conservatively, assumed to be tRCD + tCL + tRP. The default values for tRAS are chosen to match the previous behaviour and will be updated later. Diffs ----- src/mem/SimpleDRAM.py 3de4393f5649 src/mem/simple_dram.hh 3de4393f5649 src/mem/simple_dram.cc 3de4393f5649 Diff: http://reviews.gem5.org/r/2043/diff/ Testing ------- All regressions pass Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
