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Review request for Default. Repository: gem5 Description ------- Changeset 9915:eeddad2f38d9 --------------------------- mem: Schedule time for DRAM event taking tRAS into account This patch changes the time the controller is woken up to take the next scheduling decisions. tRAS is now handled in estimateLatency and doDRAMAccess and we do not need to worry about it at scheduling time. The earliest we need to wake up is to do a pre-charge, row access and column access before the bus becomes free for use. Diffs ----- src/mem/simple_dram.cc 3de4393f5649 Diff: http://reviews.gem5.org/r/2044/diff/ Testing ------- All regressions pass (with stats update) Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
