changeset 2c7219e2d999 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=2c7219e2d999
description:
cpu: rename *_DepTag constants to *_Reg_Base
Make these names more meaningful.
Specifically, made these substitutions:
s/FP_Base_DepTag/FP_Reg_Base/g;
s/Ctrl_Base_DepTag/Misc_Reg_Base/g;
s/Max_DepTag/Max_Reg_Index/g;
diffstat:
src/arch/alpha/isa/fp.isa | 2 +-
src/arch/alpha/isa/main.isa | 6 +++---
src/arch/alpha/registers.hh | 8 ++++----
src/arch/arm/insts/misc.cc | 4 ++--
src/arch/arm/insts/vfp.cc | 22 +++++++++++-----------
src/arch/arm/registers.hh | 6 +++---
src/arch/isa_parser.py | 8 ++++----
src/arch/mips/isa/base.isa | 4 ++--
src/arch/mips/isa/decoder.isa | 18 +++++++++---------
src/arch/mips/isa/formats/mt.isa | 2 +-
src/arch/mips/mt.hh | 16 ++++++++--------
src/arch/mips/registers.hh | 6 +++---
src/arch/power/registers.hh | 6 +++---
src/arch/sparc/isa/base.isa | 10 +++++-----
src/arch/sparc/registers.hh | 6 +++---
src/arch/x86/registers.hh | 8 ++++----
src/cpu/checker/cpu.hh | 12 ++++++------
src/cpu/checker/cpu_impl.hh | 4 ++--
src/cpu/inorder/resources/use_def.cc | 16 ++++++++--------
src/cpu/o3/dyn_inst.hh | 4 ++--
src/cpu/o3/rename_impl.hh | 8 ++++----
src/cpu/ozone/cpu_impl.hh | 10 +++++-----
src/cpu/reg_class.hh | 10 +++++-----
src/cpu/simple/base.hh | 12 ++++++------
24 files changed, 104 insertions(+), 104 deletions(-)
diffs (truncated from 785 to 300 lines):
diff -r 7274310be1bb -r 2c7219e2d999 src/arch/alpha/isa/fp.isa
--- a/src/arch/alpha/isa/fp.isa Tue Oct 15 14:22:43 2013 -0400
+++ b/src/arch/alpha/isa/fp.isa Tue Oct 15 14:22:43 2013 -0400
@@ -149,7 +149,7 @@
#ifndef SS_COMPATIBLE_DISASSEMBLY
std::string suffix("");
- suffix += ((_destRegIdx[0] >= FP_Base_DepTag)
+ suffix += ((_destRegIdx[0] >= FP_Reg_Base)
? fpTrappingModeSuffix[trappingMode]
: intTrappingModeSuffix[trappingMode]);
suffix += roundingModeSuffix[roundingMode];
diff -r 7274310be1bb -r 2c7219e2d999 src/arch/alpha/isa/main.isa
--- a/src/arch/alpha/isa/main.isa Tue Oct 15 14:22:43 2013 -0400
+++ b/src/arch/alpha/isa/main.isa Tue Oct 15 14:22:43 2013 -0400
@@ -224,7 +224,7 @@
/// this class and derived classes. Maybe these should really
/// live here and not in the AlphaISA namespace.
enum DependenceTags {
- FP_Base_DepTag = AlphaISA::FP_Base_DepTag
+ FP_Reg_Base = AlphaISA::FP_Reg_Base
};
/// Constructor.
@@ -253,11 +253,11 @@
void
AlphaStaticInst::printReg(std::ostream &os, int reg) const
{
- if (reg < FP_Base_DepTag) {
+ if (reg < FP_Reg_Base) {
ccprintf(os, "r%d", reg);
}
else {
- ccprintf(os, "f%d", reg - FP_Base_DepTag);
+ ccprintf(os, "f%d", reg - FP_Reg_Base);
}
}
diff -r 7274310be1bb -r 2c7219e2d999 src/arch/alpha/registers.hh
--- a/src/arch/alpha/registers.hh Tue Oct 15 14:22:43 2013 -0400
+++ b/src/arch/alpha/registers.hh Tue Oct 15 14:22:43 2013 -0400
@@ -99,10 +99,10 @@
// These enumerate all the registers for dependence tracking.
enum DependenceTags {
// 0..31 are the integer regs 0..31
- // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
- FP_Base_DepTag = NumIntRegs,
- Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs,
- Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs + NumInternalProcRegs
+ // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Reg_Base)
+ FP_Reg_Base = NumIntRegs,
+ Misc_Reg_Base = FP_Reg_Base + NumFloatRegs,
+ Max_Reg_Index = Misc_Reg_Base + NumMiscRegs + NumInternalProcRegs
};
} // namespace AlphaISA
diff -r 7274310be1bb -r 2c7219e2d999 src/arch/arm/insts/misc.cc
--- a/src/arch/arm/insts/misc.cc Tue Oct 15 14:22:43 2013 -0400
+++ b/src/arch/arm/insts/misc.cc Tue Oct 15 14:22:43 2013 -0400
@@ -80,10 +80,10 @@
bool foundPsr = false;
for (unsigned i = 0; i < numDestRegs(); i++) {
int idx = destRegIdx(i);
- if (idx < Ctrl_Base_DepTag) {
+ if (idx < Misc_Reg_Base) {
continue;
}
- idx -= Ctrl_Base_DepTag;
+ idx -= Misc_Reg_Base;
if (idx == MISCREG_CPSR) {
os << "cpsr_";
foundPsr = true;
diff -r 7274310be1bb -r 2c7219e2d999 src/arch/arm/insts/vfp.cc
--- a/src/arch/arm/insts/vfp.cc Tue Oct 15 14:22:43 2013 -0400
+++ b/src/arch/arm/insts/vfp.cc Tue Oct 15 14:22:43 2013 -0400
@@ -50,9 +50,9 @@
{
std::stringstream ss;
printMnemonic(ss);
- printReg(ss, dest + FP_Base_DepTag);
+ printReg(ss, dest + FP_Reg_Base);
ss << ", ";
- printReg(ss, op1 + FP_Base_DepTag);
+ printReg(ss, op1 + FP_Reg_Base);
return ss.str();
}
@@ -61,7 +61,7 @@
{
std::stringstream ss;
printMnemonic(ss);
- printReg(ss, dest + FP_Base_DepTag);
+ printReg(ss, dest + FP_Reg_Base);
ccprintf(ss, ", #%d", imm);
return ss.str();
}
@@ -71,9 +71,9 @@
{
std::stringstream ss;
printMnemonic(ss);
- printReg(ss, dest + FP_Base_DepTag);
+ printReg(ss, dest + FP_Reg_Base);
ss << ", ";
- printReg(ss, op1 + FP_Base_DepTag);
+ printReg(ss, op1 + FP_Reg_Base);
ccprintf(ss, ", #%d", imm);
return ss.str();
}
@@ -83,11 +83,11 @@
{
std::stringstream ss;
printMnemonic(ss);
- printReg(ss, dest + FP_Base_DepTag);
+ printReg(ss, dest + FP_Reg_Base);
ss << ", ";
- printReg(ss, op1 + FP_Base_DepTag);
+ printReg(ss, op1 + FP_Reg_Base);
ss << ", ";
- printReg(ss, op2 + FP_Base_DepTag);
+ printReg(ss, op2 + FP_Reg_Base);
return ss.str();
}
@@ -96,11 +96,11 @@
{
std::stringstream ss;
printMnemonic(ss);
- printReg(ss, dest + FP_Base_DepTag);
+ printReg(ss, dest + FP_Reg_Base);
ss << ", ";
- printReg(ss, op1 + FP_Base_DepTag);
+ printReg(ss, op1 + FP_Reg_Base);
ss << ", ";
- printReg(ss, op2 + FP_Base_DepTag);
+ printReg(ss, op2 + FP_Reg_Base);
ccprintf(ss, ", #%d", imm);
return ss.str();
}
diff -r 7274310be1bb -r 2c7219e2d999 src/arch/arm/registers.hh
--- a/src/arch/arm/registers.hh Tue Oct 15 14:22:43 2013 -0400
+++ b/src/arch/arm/registers.hh Tue Oct 15 14:22:43 2013 -0400
@@ -101,9 +101,9 @@
const int SyscallSuccessReg = ReturnValueReg;
// These help enumerate all the registers for dependence tracking.
-const int FP_Base_DepTag = NumIntRegs * (MODE_MAXMODE + 1);
-const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
-const int Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs;
+const int FP_Reg_Base = NumIntRegs * (MODE_MAXMODE + 1);
+const int Misc_Reg_Base = FP_Reg_Base + NumFloatRegs;
+const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
typedef union {
IntReg intreg;
diff -r 7274310be1bb -r 2c7219e2d999 src/arch/isa_parser.py
--- a/src/arch/isa_parser.py Tue Oct 15 14:22:43 2013 -0400
+++ b/src/arch/isa_parser.py Tue Oct 15 14:22:43 2013 -0400
@@ -610,12 +610,12 @@
c_dest = ''
if self.is_src:
- c_src = '\n\t_srcRegIdx[_numSrcRegs++] = %s + FP_Base_DepTag;' % \
+ c_src = '\n\t_srcRegIdx[_numSrcRegs++] = %s + FP_Reg_Base;' % \
(self.reg_spec)
if self.is_dest:
c_dest = \
- '\n\t_destRegIdx[_numDestRegs++] = %s + FP_Base_DepTag;' % \
+ '\n\t_destRegIdx[_numDestRegs++] = %s + FP_Reg_Base;' % \
(self.reg_spec)
c_dest += '\n\t_numFPDestRegs++;'
@@ -673,12 +673,12 @@
if self.is_src:
c_src = \
- '\n\t_srcRegIdx[_numSrcRegs++] = %s + Ctrl_Base_DepTag;' % \
+ '\n\t_srcRegIdx[_numSrcRegs++] = %s + Misc_Reg_Base;' % \
(self.reg_spec)
if self.is_dest:
c_dest = \
- '\n\t_destRegIdx[_numDestRegs++] = %s + Ctrl_Base_DepTag;' % \
+ '\n\t_destRegIdx[_numDestRegs++] = %s + Misc_Reg_Base;' % \
(self.reg_spec)
return c_src + c_dest
diff -r 7274310be1bb -r 2c7219e2d999 src/arch/mips/isa/base.isa
--- a/src/arch/mips/isa/base.isa Tue Oct 15 14:22:43 2013 -0400
+++ b/src/arch/mips/isa/base.isa Tue Oct 15 14:22:43 2013 -0400
@@ -72,11 +72,11 @@
void MipsStaticInst::printReg(std::ostream &os, int reg) const
{
- if (reg < FP_Base_DepTag) {
+ if (reg < FP_Reg_Base) {
ccprintf(os, "r%d", reg);
}
else {
- ccprintf(os, "f%d", reg - FP_Base_DepTag);
+ ccprintf(os, "f%d", reg - FP_Reg_Base);
}
}
diff -r 7274310be1bb -r 2c7219e2d999 src/arch/mips/isa/decoder.isa
--- a/src/arch/mips/isa/decoder.isa Tue Oct 15 14:22:43 2013 -0400
+++ b/src/arch/mips/isa/decoder.isa Tue Oct 15 14:22:43 2013 -0400
@@ -385,7 +385,7 @@
0x8: decode MT_U {
0x0: mftc0({{
data = xc->readRegOtherThread((RT << 3 | SEL) +
- Ctrl_Base_DepTag);
+ Misc_Reg_Base);
}});
0x1: decode SEL {
0x0: mftgpr({{
@@ -409,19 +409,19 @@
}
0x2: decode MT_H {
0x0: mftc1({{ data = xc->readRegOtherThread(RT
+
-
FP_Base_DepTag);
+
FP_Reg_Base);
}});
0x1: mfthc1({{ data =
xc->readRegOtherThread(RT +
-
FP_Base_DepTag);
+
FP_Reg_Base);
}});
}
0x3: cftc1({{
uint32_t fcsr_val =
xc->readRegOtherThread(FLOATREG_FCSR +
-
FP_Base_DepTag);
+
FP_Reg_Base);
switch (RT) {
case 0:
data = xc->readRegOtherThread(FLOATREG_FIR
+
-
Ctrl_Base_DepTag);
+
Misc_Reg_Base);
break;
case 25:
data = (fcsr_val & 0xFE000000 >> 24) |
@@ -450,7 +450,7 @@
format MT_MTTR {
// Decode MIPS MT MTTR instruction into sub-instructions
0xC: decode MT_U {
- 0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) +
Ctrl_Base_DepTag,
+ 0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) +
Misc_Reg_Base,
Rt);
}});
0x1: decode SEL {
@@ -496,10 +496,10 @@
}
0x2: mttc1({{
uint64_t data = xc->readRegOtherThread(RD +
-
FP_Base_DepTag);
+
FP_Reg_Base);
data = insertBits(data, MT_H ? 63 : 31,
MT_H ? 32 : 0, Rt);
- xc->setRegOtherThread(RD + FP_Base_DepTag,
+ xc->setRegOtherThread(RD + FP_Reg_Base,
data);
}});
0x3: cttc1({{
@@ -534,7 +534,7 @@
"Access to Floating Control "
"S""tatus Register", FS);
}
- xc->setRegOtherThread(FLOATREG_FCSR +
FP_Base_DepTag, data);
+ xc->setRegOtherThread(FLOATREG_FCSR +
FP_Reg_Base, data);
}});
default: CP0Unimpl::unknown();
}
diff -r 7274310be1bb -r 2c7219e2d999 src/arch/mips/isa/formats/mt.isa
--- a/src/arch/mips/isa/formats/mt.isa Tue Oct 15 14:22:43 2013 -0400
+++ b/src/arch/mips/isa/formats/mt.isa Tue Oct 15 14:22:43 2013 -0400
@@ -102,7 +102,7 @@
MVPConf0Reg &mvp_conf0)
{
vpe_conf0 = xc->readMiscReg(MISCREG_VPE_CONF0);
- tc_bind_mt = xc->readRegOtherThread(MISCREG_TC_BIND +
Ctrl_Base_DepTag);
+ tc_bind_mt = xc->readRegOtherThread(MISCREG_TC_BIND + Misc_Reg_Base);
tc_bind = xc->readMiscReg(MISCREG_TC_BIND);
vpe_control = xc->readMiscReg(MISCREG_VPE_CONTROL);
mvp_conf0 = xc->readMiscReg(MISCREG_MVP_CONF0);
diff -r 7274310be1bb -r 2c7219e2d999 src/arch/mips/mt.hh
--- a/src/arch/mips/mt.hh Tue Oct 15 14:22:43 2013 -0400
+++ b/src/arch/mips/mt.hh Tue Oct 15 14:22:43 2013 -0400
@@ -113,23 +113,23 @@
int success = 0;
for (ThreadID tid = 0; tid < num_threads && success == 0; tid++) {
TCBindReg tidTCBind =
- tc->readRegOtherThread(MISCREG_TC_BIND + Ctrl_Base_DepTag, tid);
+ tc->readRegOtherThread(MISCREG_TC_BIND + Misc_Reg_Base, tid);
TCBindReg tcBind = tc->readMiscRegNoEffect(MISCREG_TC_BIND);
if (tidTCBind.curVPE == tcBind.curVPE) {
TCStatusReg tidTCStatus =
tc->readRegOtherThread(MISCREG_TC_STATUS +
- Ctrl_Base_DepTag,tid);
+ Misc_Reg_Base,tid);
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