changeset 803903a8dac1 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=803903a8dac1
description:
cpu/o3: clean up rename map and free list
Restructured rename map and free list to clean up some
extraneous code and separate out common code that can
be reused across different register classes (int and fp
at this point). Both components now consist of a set
of Simple* objects that are stand-alone rename map &
free list for each class, plus a Unified* object that
presents a unified interface across all register
classes and then redirects accesses to the appropriate
Simple* object as needed.
Moved free list initialization to PhysRegFile to better
isolate knowledge of physical register index mappings
to that class (and remove the need to pass a number
of parameters to the free list constructor).
Causes a small change to these stats:
cpu.rename.int_rename_lookups
cpu.rename.fp_rename_lookups
because they are now categorized on a per-operand basis
rather than a per-instruction basis.
That is, an instruction with mixed fp/int/misc operand
types will have each operand categorized independently,
where previously the lookup was categorized based on
the instruction type.
diffstat:
src/cpu/o3/SConscript | 1 +
src/cpu/o3/cpu.cc | 86 +++++-------
src/cpu/o3/cpu.hh | 3 +-
src/cpu/o3/cpu_policy.hh | 9 +-
src/cpu/o3/free_list.cc | 41 +-----
src/cpu/o3/free_list.hh | 176 ++++++++++++--------------
src/cpu/o3/regfile.cc | 64 +++++++++
src/cpu/o3/regfile.hh | 38 ++---
src/cpu/o3/rename_impl.hh | 131 ++++++++++---------
src/cpu/o3/rename_map.cc | 278 ++++++++++++++---------------------------
src/cpu/o3/rename_map.hh | 306 ++++++++++++++++++++++++++++++++++-----------
11 files changed, 596 insertions(+), 537 deletions(-)
diffs (truncated from 1588 to 300 lines):
diff -r 2c7219e2d999 -r 803903a8dac1 src/cpu/o3/SConscript
--- a/src/cpu/o3/SConscript Tue Oct 15 14:22:43 2013 -0400
+++ b/src/cpu/o3/SConscript Tue Oct 15 14:22:44 2013 -0400
@@ -56,6 +56,7 @@
Source('lsq.cc')
Source('lsq_unit.cc')
Source('mem_dep_unit.cc')
+ Source('regfile.cc')
Source('rename.cc')
Source('rename_map.cc')
Source('rob.cc')
diff -r 2c7219e2d999 -r 803903a8dac1 src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc Tue Oct 15 14:22:43 2013 -0400
+++ b/src/cpu/o3/cpu.cc Tue Oct 15 14:22:44 2013 -0400
@@ -227,9 +227,7 @@
regFile(params->numPhysIntRegs,
params->numPhysFloatRegs),
- freeList(params->numThreads,
- TheISA::NumIntRegs, params->numPhysIntRegs,
- TheISA::NumFloatRegs, params->numPhysFloatRegs),
+ freeList(name() + ".freelist", ®File),
rob(this,
params->numROBEntries, params->squashWidth,
@@ -334,56 +332,46 @@
iew.setScoreboard(&scoreboard);
// Setup the rename map for whichever stages need it.
- PhysRegIndex lreg_idx = 0;
- PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
-
for (ThreadID tid = 0; tid < numThreads; tid++) {
- bool bindRegs = (tid <= active_threads - 1);
-
isa[tid] = params->isa[tid];
- commitRenameMap[tid].init(TheISA::NumIntRegs,
- params->numPhysIntRegs,
- lreg_idx, //Index for Logical.
Regs
+ // Only Alpha has an FP zero register, so for other ISAs we
+ // use an invalid FP register index to avoid special treatment
+ // of any valid FP reg.
+ RegIndex invalidFPReg = TheISA::NumFloatRegs + 1;
+ RegIndex fpZeroReg =
+ (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg;
- TheISA::NumFloatRegs,
- params->numPhysFloatRegs,
- freg_idx, //Index for Float Regs
+ commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
+ &freeList);
- TheISA::NumMiscRegs,
-
- TheISA::ZeroReg,
- TheISA::ZeroReg,
-
- tid,
- false);
-
- renameMap[tid].init(TheISA::NumIntRegs,
- params->numPhysIntRegs,
- lreg_idx, //Index for Logical.
Regs
-
- TheISA::NumFloatRegs,
- params->numPhysFloatRegs,
- freg_idx, //Index for Float Regs
-
- TheISA::NumMiscRegs,
-
- TheISA::ZeroReg,
- TheISA::ZeroReg,
-
- tid,
- bindRegs);
+ renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
+ &freeList);
activateThreadEvent[tid].init(tid, this);
deallocateContextEvent[tid].init(tid, this);
}
+ // Initialize rename map to assign physical registers to the
+ // architectural registers for active threads only.
+ for (ThreadID tid = 0; tid < active_threads; tid++) {
+ for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
+ // Note that we can't use the rename() method because we don't
+ // want special treatment for the zero register at this point
+ PhysRegIndex phys_reg = freeList.getIntReg();
+ renameMap[tid].setIntEntry(ridx, phys_reg);
+ commitRenameMap[tid].setIntEntry(ridx, phys_reg);
+ }
+
+ for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
+ PhysRegIndex phys_reg = freeList.getFloatReg();
+ renameMap[tid].setFloatEntry(ridx, phys_reg);
+ commitRenameMap[tid].setFloatEntry(ridx, phys_reg);
+ }
+ }
+
rename.setRenameMap(renameMap);
commit.setRenameMap(commitRenameMap);
-
- // Give renameMap & rename stage access to the freeList;
- for (ThreadID tid = 0; tid < numThreads; tid++)
- renameMap[tid].setFreeList(&freeList);
rename.setFreeList(&freeList);
// Setup the ROB for whichever stages need it.
@@ -1406,7 +1394,7 @@
FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
{
intRegfileReads++;
- PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
+ PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
return regFile.readIntReg(phys_reg);
}
@@ -1416,8 +1404,7 @@
FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
{
fpRegfileReads++;
- int idx = reg_idx + TheISA::NumIntRegs;
- PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
+ PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
return regFile.readFloatReg(phys_reg);
}
@@ -1427,8 +1414,7 @@
FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
{
fpRegfileReads++;
- int idx = reg_idx + TheISA::NumIntRegs;
- PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
+ PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
return regFile.readFloatRegBits(phys_reg);
}
@@ -1438,7 +1424,7 @@
FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
{
intRegfileWrites++;
- PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
+ PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
regFile.setIntReg(phys_reg, val);
}
@@ -1448,8 +1434,7 @@
FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
{
fpRegfileWrites++;
- int idx = reg_idx + TheISA::NumIntRegs;
- PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
+ PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
regFile.setFloatReg(phys_reg, val);
}
@@ -1459,8 +1444,7 @@
FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
{
fpRegfileWrites++;
- int idx = reg_idx + TheISA::NumIntRegs;
- PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
+ PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
regFile.setFloatRegBits(phys_reg, val);
}
diff -r 2c7219e2d999 -r 803903a8dac1 src/cpu/o3/cpu.hh
--- a/src/cpu/o3/cpu.hh Tue Oct 15 14:22:43 2013 -0400
+++ b/src/cpu/o3/cpu.hh Tue Oct 15 14:22:44 2013 -0400
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2011-2013 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -655,7 +656,7 @@
typename CPUPolicy::Commit commit;
/** The register file. */
- typename CPUPolicy::RegFile regFile;
+ PhysRegFile regFile;
/** The free list. */
typename CPUPolicy::FreeList freeList;
diff -r 2c7219e2d999 -r 803903a8dac1 src/cpu/o3/cpu_policy.hh
--- a/src/cpu/o3/cpu_policy.hh Tue Oct 15 14:22:43 2013 -0400
+++ b/src/cpu/o3/cpu_policy.hh Tue Oct 15 14:22:44 2013 -0400
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -59,14 +60,10 @@
template<class Impl>
struct SimpleCPUPolicy
{
- /** Typedef for the register file. Most classes assume a unified
- * physical register file.
- */
- typedef PhysRegFile RegFile;
/** Typedef for the freelist of registers. */
- typedef SimpleFreeList FreeList;
+ typedef UnifiedFreeList FreeList;
/** Typedef for the rename map. */
- typedef SimpleRenameMap RenameMap;
+ typedef UnifiedRenameMap RenameMap;
/** Typedef for the ROB. */
typedef ::ROB<Impl> ROB;
/** Typedef for the instruction queue/scheduler. */
diff -r 2c7219e2d999 -r 803903a8dac1 src/cpu/o3/free_list.cc
--- a/src/cpu/o3/free_list.cc Tue Oct 15 14:22:43 2013 -0400
+++ b/src/cpu/o3/free_list.cc Tue Oct 15 14:22:44 2013 -0400
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -32,41 +33,13 @@
#include "cpu/o3/free_list.hh"
#include "debug/FreeList.hh"
-SimpleFreeList::SimpleFreeList(ThreadID activeThreads,
- unsigned _numLogicalIntRegs,
- unsigned _numPhysicalIntRegs,
- unsigned _numLogicalFloatRegs,
- unsigned _numPhysicalFloatRegs)
- : numLogicalIntRegs(_numLogicalIntRegs),
- numPhysicalIntRegs(_numPhysicalIntRegs),
- numLogicalFloatRegs(_numLogicalFloatRegs),
- numPhysicalFloatRegs(_numPhysicalFloatRegs),
- numPhysicalRegs(numPhysicalIntRegs + numPhysicalFloatRegs)
+UnifiedFreeList::UnifiedFreeList(const std::string &_my_name,
+ PhysRegFile *_regFile)
+ : _name(_my_name), regFile(_regFile)
{
DPRINTF(FreeList, "Creating new free list object.\n");
- // Put all of the extra physical registers onto the free list. This
- // means excluding all of the base logical registers.
- for (PhysRegIndex i = numLogicalIntRegs * activeThreads;
- i < numPhysicalIntRegs; ++i)
- {
- freeIntRegs.push(i);
- }
-
- // Put all of the extra physical registers onto the free list. This
- // means excluding all of the base logical registers. Because the
- // float registers' indices start where the physical registers end,
- // some math must be done to determine where the free registers start.
- PhysRegIndex i = numPhysicalIntRegs + (numLogicalFloatRegs *
activeThreads);
-
- for ( ; i < numPhysicalRegs; ++i)
- {
- freeFloatRegs.push(i);
- }
+ // Have the register file initialize the free list since it knows
+ // about its internal organization
+ regFile->initFreeList(this);
}
-
-std::string
-SimpleFreeList::name() const
-{
- return "cpu.freelist";
-}
diff -r 2c7219e2d999 -r 803903a8dac1 src/cpu/o3/free_list.hh
--- a/src/cpu/o3/free_list.hh Tue Oct 15 14:22:43 2013 -0400
+++ b/src/cpu/o3/free_list.hh Tue Oct 15 14:22:44 2013 -0400
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -34,14 +35,51 @@
#include <iostream>
#include <queue>
-#include "arch/registers.hh"
#include "base/misc.hh"
#include "base/trace.hh"
-#include "config/the_isa.hh"
#include "cpu/o3/comm.hh"
+#include "cpu/o3/regfile.hh"
#include "debug/FreeList.hh"
/**
+ * Free list for a single class of registers (e.g., integer
+ * or floating point). Because the register class is implicitly
+ * determined by the rename map instance being accessed, all
+ * architectural register index parameters and values in this class
+ * are relative (e.g., %fp2 is just index 2).
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