changeset 9a41f7f07da5 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9a41f7f07da5
description:
dev: Allow additional UART interrupts to be set
This patch allows setting a few additional interrupts for status
changes that should never occur.
diffstat:
src/dev/arm/pl011.cc | 8 ++++++--
1 files changed, 6 insertions(+), 2 deletions(-)
diffs (20 lines):
diff -r 45a013c50eff -r 9a41f7f07da5 src/dev/arm/pl011.cc
--- a/src/dev/arm/pl011.cc Thu Oct 17 10:20:45 2013 -0500
+++ b/src/dev/arm/pl011.cc Thu Oct 17 10:20:45 2013 -0500
@@ -211,10 +211,14 @@
case UART_IMSC:
imsc = data;
- if (imsc.rimim || imsc.ctsmim || imsc.dcdmim || imsc.dsrmim
- || imsc.feim || imsc.peim || imsc.beim || imsc.oeim || imsc.rsvd)
+ if (imsc.feim || imsc.peim || imsc.beim || imsc.oeim || imsc.rsvd)
panic("Unknown interrupt enabled\n");
+ // rimim, ctsmim, dcdmim, dsrmim can be enabled but are ignored
+ // they are supposed to interrupt on a change of status in the line
+ // which we should never have since our terminal is happy to always
+ // receive bytes.
+
if (imsc.txim) {
DPRINTF(Uart, "Writing to IMSC: TX int enabled, scheduling
interruptt\n");
rawInt.txim = 1;
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