[gem5-dev] changeset in gem5: config: Fix memtest example script

[Ali Saidi]

changeset 9d3b979cd3ed in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9d3b979cd3ed
description:
        config: Fix memtest example script

diffstat:

 configs/example/memtest.py |  13 +++++++++++--
 1 files changed, 11 insertions(+), 2 deletions(-)

diffs (37 lines):

diff -r 9a41f7f07da5 -r 9d3b979cd3ed configs/example/memtest.py
--- a/configs/example/memtest.py        Thu Oct 17 10:20:45 2013 -0500
+++ b/configs/example/memtest.py        Thu Oct 17 10:20:45 2013 -0500
@@ -83,6 +83,10 @@
                   metavar="NLOADS",
                   help="Progress message interval "
                   "[default: %default]")
+parser.add_option("--sys-clock", action="store", type="string",
+                  default='1GHz',
+                  help = """Top-level clock for blocks running at system
+                  speed""")
 
 (options, args) = parser.parse_args()
 
@@ -110,7 +114,7 @@
 
 # define prototype L1 cache
 proto_l1 = BaseCache(size = '32kB', assoc = 4,
-                     hit_latency = '1ns', response_latency = '1ns',
+                     hit_latency = 1, response_latency = 1,
                      tgts_per_mshr = 8)
 
 if options.blocking:
@@ -145,7 +149,12 @@
                 funcbus = NoncoherentBus(),
                 physmem = SimpleMemory(latency = "100ns"),
                 cache_line_size = block_size)
-system.clk_domain = SrcClockDomain(clock =  options.sys_clock)
+
+
+system.voltage_domain = VoltageDomain(voltage = '1V')
+
+system.clk_domain = SrcClockDomain(clock =  options.sys_clock,
+                        voltage_domain = system.voltage_domain)
 
 def make_level(spec, prototypes, attach_obj, attach_port):
      fanout = spec[0]
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