changeset f00546aff354 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f00546aff354
description:
        cpu: Put in assertions to check for maximum supported LQ/SQ size

        LSQSenderState represents the LQ/SQ index using uint8_t, which supports 
up to
         256 entries (including the sentinel entry). Sending packets to memory 
with a
        higher index than 255 truncates the index, such that the response 
matches the
        wrong entry. For instance, this can result in a deadlock if a store 
completion
        does not clear the head entry.

diffstat:

 src/cpu/o3/lsq_unit_impl.hh |  7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diffs (31 lines):

diff -r cc9dc514036e -r f00546aff354 src/cpu/o3/lsq_unit_impl.hh
--- a/src/cpu/o3/lsq_unit_impl.hh       Thu Oct 17 10:20:45 2013 -0500
+++ b/src/cpu/o3/lsq_unit_impl.hh       Thu Oct 17 10:20:45 2013 -0500
@@ -158,6 +158,10 @@
     LQEntries = maxLQEntries + 1;
     SQEntries = maxSQEntries + 1;
 
+    //Due to uint8_t index in LSQSenderState
+    assert(LQEntries <= 256);
+    assert(SQEntries <= 256);
+
     loadQueue.resize(LQEntries);
     storeQueue.resize(SQEntries);
 
@@ -306,6 +310,7 @@
         LQEntries = size_plus_sentinel;
     }
 
+    assert(LQEntries <= 256);
 }
 
 template<class Impl>
@@ -322,6 +327,8 @@
     } else {
         SQEntries = size_plus_sentinel;
     }
+
+    assert(SQEntries <= 256);
 }
 
 template <class Impl>
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev

Reply via email to