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Review request for Default. Repository: gem5 Description ------- Changeset 10009:00ecc33c134a --------------------------- arch, cpu: Add support for flattening misc register indexes. With ARMv8 support the same misc register id results in accessing different registers depending on the current mode of the processor. This patch adds the same orthogonality to the misc register file as the others (int, float, cc). For all the othre ISAs this is currently a null-implementation. Additionally, a system variable is added to all the ISA objects. Diffs ----- src/arch/alpha/AlphaISA.py 81d7551dd3be src/arch/alpha/isa.hh 81d7551dd3be src/arch/alpha/isa.cc 81d7551dd3be src/arch/mips/MipsISA.py 81d7551dd3be src/arch/mips/isa.hh 81d7551dd3be src/arch/mips/isa.cc 81d7551dd3be src/arch/power/isa.hh 81d7551dd3be src/arch/sparc/isa.hh 81d7551dd3be src/arch/x86/isa.hh 81d7551dd3be src/cpu/checker/thread_context.hh 81d7551dd3be src/cpu/inorder/thread_context.hh 81d7551dd3be src/cpu/o3/thread_context.hh 81d7551dd3be src/cpu/o3/thread_context_impl.hh 81d7551dd3be src/cpu/simple_thread.hh 81d7551dd3be src/cpu/thread_context.hh 81d7551dd3be Diff: http://reviews.gem5.org/r/2104/diff/ Testing ------- Thanks, Ali Saidi _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
