----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2103/ -----------------------------------------------------------
Review request for Default. Repository: gem5 Description ------- Changeset 10008:4573823d8cd7 --------------------------- cpu: Add support for Memory+Barrier instruction types in O3 cpu. Diffs ----- src/cpu/o3/inst_queue_impl.hh 81d7551dd3be Diff: http://reviews.gem5.org/r/2103/diff/ Testing ------- Thanks, Ali Saidi _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
