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Review request for Default. Repository: gem5 Description ------- Changeset 10007:7b245b85f5c3 --------------------------- cpu: Add support for instructions that zero cache lines. Diffs ----- src/cpu/base_dyn_inst_impl.hh 81d7551dd3be src/cpu/o3/lsq_unit.hh 81d7551dd3be src/cpu/o3/lsq_unit_impl.hh 81d7551dd3be src/cpu/simple/atomic.cc 81d7551dd3be src/cpu/simple/timing.cc 81d7551dd3be src/mem/request.hh 81d7551dd3be Diff: http://reviews.gem5.org/r/2107/diff/ Testing ------- Thanks, Ali Saidi _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
