changeset fc10e1f9f124 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=fc10e1f9f124
description:
mem: per-thread cache occupancy and per-block ages
This patch enables tracking of cache occupancy per thread along with
ages (in buckets) per cache blocks. Cache occupancy stats are
recalculated on each stat dump.
diffstat:
src/arch/arm/table_walker.cc | 2 ++
src/arch/arm/tlb.cc | 3 +++
src/cpu/base_dyn_inst.hh | 4 ++++
src/cpu/o3/fetch_impl.hh | 2 ++
src/cpu/simple/atomic.cc | 3 +++
src/cpu/simple/timing.cc | 5 +++++
src/dev/dma_device.cc | 1 +
src/mem/cache/blk.hh | 12 ++++++++++--
src/mem/cache/cache_impl.hh | 6 ++++++
src/mem/cache/prefetch/base.cc | 1 +
src/mem/cache/tags/base.cc | 23 +++++++++++++++++++++++
src/mem/cache/tags/base.hh | 22 ++++++++++++++++++++++
src/mem/cache/tags/lru.cc | 40 ++++++++++++++++++++++++++++++++++++++++
src/mem/cache/tags/lru.hh | 5 +++++
src/mem/request.hh | 23 ++++++++++++++++++++++-
15 files changed, 149 insertions(+), 3 deletions(-)
diffs (truncated from 447 to 300 lines):
diff -r 91faf6649de0 -r fc10e1f9f124 src/arch/arm/table_walker.cc
--- a/src/arch/arm/table_walker.cc Fri Jan 24 15:29:30 2014 -0600
+++ b/src/arch/arm/table_walker.cc Fri Jan 24 15:29:30 2014 -0600
@@ -308,6 +308,7 @@
f = currState->fault;
} else {
RequestPtr req = new Request(l1desc_addr, sizeof(uint32_t), flag,
masterId);
+ req->taskId(ContextSwitchTaskId::DMA);
PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
pkt->dataStatic((uint8_t*)&currState->l1Desc.data);
port.sendFunctional(pkt);
@@ -653,6 +654,7 @@
} else {
RequestPtr req = new Request(l2desc_addr, sizeof(uint32_t), 0,
masterId);
+ req->taskId(ContextSwitchTaskId::DMA);
PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
pkt->dataStatic((uint8_t*)&currState->l2Desc.data);
port.sendFunctional(pkt);
diff -r 91faf6649de0 -r fc10e1f9f124 src/arch/arm/tlb.cc
--- a/src/arch/arm/tlb.cc Fri Jan 24 15:29:30 2014 -0600
+++ b/src/arch/arm/tlb.cc Fri Jan 24 15:29:30 2014 -0600
@@ -54,6 +54,7 @@
#include "base/inifile.hh"
#include "base/str.hh"
#include "base/trace.hh"
+#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/Checkpoint.hh"
#include "debug/TLB.hh"
@@ -477,6 +478,8 @@
if (is_priv)
req->setFlags(Request::PRIVILEGED);
+ req->taskId(tc->getCpuPtr()->taskId());
+
DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d\n",
isPriv, flags & UserMode);
// If this is a clrex instruction, provide a PA of 0 with no fault
diff -r 91faf6649de0 -r fc10e1f9f124 src/cpu/base_dyn_inst.hh
--- a/src/cpu/base_dyn_inst.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/cpu/base_dyn_inst.hh Fri Jan 24 15:29:30 2014 -0600
@@ -890,6 +890,8 @@
req = new Request(asid, addr, size, flags, masterId(),
this->pc.instAddr(),
thread->contextId(), threadNumber);
+ req->taskId(cpu->taskId());
+
// Only split the request if the ISA supports unaligned accesses.
if (TheISA::HasUnalignedMemAcc) {
splitRequest(req, sreqLow, sreqHigh);
@@ -953,6 +955,8 @@
req = new Request(asid, addr, size, flags, masterId(),
this->pc.instAddr(),
thread->contextId(), threadNumber);
+ req->taskId(cpu->taskId());
+
// Only split the request if the ISA supports unaligned accesses.
if (TheISA::HasUnalignedMemAcc) {
splitRequest(req, sreqLow, sreqHigh);
diff -r 91faf6649de0 -r fc10e1f9f124 src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/cpu/o3/fetch_impl.hh Fri Jan 24 15:29:30 2014 -0600
@@ -604,6 +604,8 @@
Request::INST_FETCH, cpu->instMasterId(), pc,
cpu->thread[tid]->contextId(), tid);
+ mem_req->taskId(cpu->taskId());
+
memReq[tid] = mem_req;
// Initiate translation of the icache block
diff -r 91faf6649de0 -r fc10e1f9f124 src/cpu/simple/atomic.cc
--- a/src/cpu/simple/atomic.cc Fri Jan 24 15:29:30 2014 -0600
+++ b/src/cpu/simple/atomic.cc Fri Jan 24 15:29:30 2014 -0600
@@ -301,6 +301,7 @@
dcache_latency = 0;
+ req->taskId(taskId());
while (1) {
req->setVirt(0, addr, size, flags, dataMasterId(),
thread->pcState().instAddr());
@@ -387,6 +388,7 @@
dcache_latency = 0;
+ req->taskId(taskId());
while(1) {
req->setVirt(0, addr, size, flags, dataMasterId(),
thread->pcState().instAddr());
@@ -492,6 +494,7 @@
bool needToFetch = !isRomMicroPC(pcState.microPC()) &&
!curMacroStaticInst;
if (needToFetch) {
+ ifetch_req.taskId(taskId());
setupFetchRequest(&ifetch_req);
fault = thread->itb->translateAtomic(&ifetch_req, tc,
BaseTLB::Execute);
diff -r 91faf6649de0 -r fc10e1f9f124 src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc Fri Jan 24 15:29:30 2014 -0600
+++ b/src/cpu/simple/timing.cc Fri Jan 24 15:29:30 2014 -0600
@@ -415,6 +415,8 @@
RequestPtr req = new Request(asid, addr, size,
flags, dataMasterId(), pc, _cpuId, tid);
+ req->taskId(taskId());
+
Addr split_addr = roundDown(addr + size - 1, block_size);
assert(split_addr <= addr || split_addr - addr < block_size);
@@ -484,6 +486,8 @@
RequestPtr req = new Request(asid, addr, size,
flags, dataMasterId(), pc, _cpuId, tid);
+ req->taskId(taskId());
+
Addr split_addr = roundDown(addr + size - 1, block_size);
assert(split_addr <= addr || split_addr - addr < block_size);
@@ -561,6 +565,7 @@
if (needToFetch) {
_status = BaseSimpleCPU::Running;
Request *ifetch_req = new Request();
+ ifetch_req->taskId(taskId());
ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
setupFetchRequest(ifetch_req);
DPRINTF(SimpleCPU, "Translating address %#x\n",
ifetch_req->getVaddr());
diff -r 91faf6649de0 -r fc10e1f9f124 src/dev/dma_device.cc
--- a/src/dev/dma_device.cc Fri Jan 24 15:29:30 2014 -0600
+++ b/src/dev/dma_device.cc Fri Jan 24 15:29:30 2014 -0600
@@ -166,6 +166,7 @@
for (ChunkGenerator gen(addr, size, sys->cacheLineSize());
!gen.done(); gen.next()) {
Request *req = new Request(gen.addr(), gen.size(), flag, masterId);
+ req->taskId(ContextSwitchTaskId::DMA);
PacketPtr pkt = new Packet(req, cmd);
// Increment the data pointer on a write
diff -r 91faf6649de0 -r fc10e1f9f124 src/mem/cache/blk.hh
--- a/src/mem/cache/blk.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/mem/cache/blk.hh Fri Jan 24 15:29:30 2014 -0600
@@ -80,6 +80,9 @@
class CacheBlk
{
public:
+ /** Task Id associated with this block */
+ uint32_t task_id;
+
/** The address space ID of this block. */
int asid;
/** Data block tag value. */
@@ -119,6 +122,8 @@
/** holds the source requestor ID for this block. */
int srcMasterId;
+ Tick tickInserted;
+
protected:
/**
* Represents that the indicated thread context has a "lock" on
@@ -162,9 +167,11 @@
public:
CacheBlk()
- : asid(-1), tag(0), data(0) ,size(0), status(0), whenReady(0),
+ : task_id(ContextSwitchTaskId::Unknown),
+ asid(-1), tag(0), data(0) ,size(0), status(0), whenReady(0),
set(-1), isTouched(false), refCount(0),
- srcMasterId(Request::invldMasterId)
+ srcMasterId(Request::invldMasterId),
+ tickInserted(0)
{}
/**
@@ -182,6 +189,7 @@
whenReady = rhs.whenReady;
set = rhs.set;
refCount = rhs.refCount;
+ task_id = rhs.task_id;
return *this;
}
diff -r 91faf6649de0 -r fc10e1f9f124 src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/mem/cache/cache_impl.hh Fri Jan 24 15:29:30 2014 -0600
@@ -1074,6 +1074,11 @@
Request *writebackReq =
new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0,
Request::wbMasterId);
+
+ writebackReq->taskId(blk->task_id);
+ blk->task_id= ContextSwitchTaskId::Unknown;
+ blk->tickInserted = curTick();
+
PacketPtr writeback = new Packet(writebackReq, MemCmd::Writeback);
if (blk->isWritable()) {
writeback->setSupplyExclusive();
@@ -1120,6 +1125,7 @@
Request request(tags->regenerateBlkAddr(blk.tag, blk.set),
blkSize, 0, Request::funcMasterId);
+ request.taskId(blk.task_id);
Packet packet(&request, MemCmd::WriteReq);
packet.dataStatic(blk.data);
diff -r 91faf6649de0 -r fc10e1f9f124 src/mem/cache/prefetch/base.cc
--- a/src/mem/cache/prefetch/base.cc Fri Jan 24 15:29:30 2014 -0600
+++ b/src/mem/cache/prefetch/base.cc Fri Jan 24 15:29:30 2014 -0600
@@ -247,6 +247,7 @@
// create a prefetch memreq
Request *prefetchReq = new Request(*addrIter, blkSize, 0,
masterId);
+ prefetchReq->taskId(ContextSwitchTaskId::Prefetcher);
PacketPtr prefetch =
new Packet(prefetchReq, MemCmd::HardPFReq);
prefetch->allocate();
diff -r 91faf6649de0 -r fc10e1f9f124 src/mem/cache/tags/base.cc
--- a/src/mem/cache/tags/base.cc Fri Jan 24 15:29:30 2014 -0600
+++ b/src/mem/cache/tags/base.cc Fri Jan 24 15:29:30 2014 -0600
@@ -125,5 +125,28 @@
avgOccs = occupancies / Stats::constant(numBlocks);
+ occupanciesTaskId
+ .init(ContextSwitchTaskId::NumTaskId)
+ .name(name() + ".occ_task_id_blocks")
+ .desc("Occupied blocks per task id")
+ .flags(nozero | nonan)
+ ;
+
+ ageTaskId
+ .init(ContextSwitchTaskId::NumTaskId, 5)
+ .name(name() + ".age_task_id_blocks")
+ .desc("Occupied blocks per task id")
+ .flags(nozero | nonan)
+ ;
+
+ percentOccsTaskId
+ .name(name() + ".occ_task_id_percent")
+ .desc("Percentage of cache occupancy per task id")
+ .flags(nozero)
+ ;
+
+ percentOccsTaskId = occupanciesTaskId / Stats::constant(numBlocks);
+
+ registerDumpCallback(new BaseTagsDumpCallback(this));
registerExitCallback(new BaseTagsCallback(this));
}
diff -r 91faf6649de0 -r fc10e1f9f124 src/mem/cache/tags/base.hh
--- a/src/mem/cache/tags/base.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/mem/cache/tags/base.hh Fri Jan 24 15:29:30 2014 -0600
@@ -121,6 +121,15 @@
/** Average occ % of each requestor using the cache */
Stats::Formula avgOccs;
+ /** Occupancy of each context/cpu using the cache */
+ Stats::Vector occupanciesTaskId;
+
+ /** Occupancy of each context/cpu using the cache */
+ Stats::Vector2d ageTaskId;
+
+ /** Occ % of each context/cpu using the cache */
+ Stats::Formula percentOccsTaskId;
+
/**
* @}
*/
@@ -152,6 +161,11 @@
virtual void cleanupRefs() {}
/**
+ * Computes stats just prior to dump event
+ */
+ virtual void computeStats() {}
+
+ /**
*iterated through all blocks and clear all locks
*Needed to clear all lock tracking at once
*/
@@ -171,4 +185,12 @@
virtual void process() { tags->cleanupRefs(); };
};
+class BaseTagsDumpCallback : public Callback
+{
+ BaseTags *tags;
+ public:
+ BaseTagsDumpCallback(BaseTags *t) : tags(t) {}
+ virtual void process() { tags->computeStats(); };
+};
+
#endif //__BASE_TAGS_HH__
diff -r 91faf6649de0 -r fc10e1f9f124 src/mem/cache/tags/lru.cc
--- a/src/mem/cache/tags/lru.cc Fri Jan 24 15:29:30 2014 -0600
+++ b/src/mem/cache/tags/lru.cc Fri Jan 24 15:29:30 2014 -0600
@@ -176,6 +176,7 @@
{
Addr addr = pkt->getAddr();
MasterID master_id = pkt->req->masterId();
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