changeset 91faf6649de0 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=91faf6649de0
description:
base: add support for probe points and common probes
The probe patch is motivated by the desire to move analytical and trace
code
away from functional code. This is achieved by the probe interface
which is
essentially a glorified observer model.
What this means to users:
* add a probe point and a "notify" call at the source of an "event"
* add an isolated module, that is being used to carry out *your*
analysis (e.g. generate a trace)
* register that module as a probe listener
Note: an example is given for reference in
src/cpu/o3/simple_trace.[hh|cc] and src/cpu/SimpleTrace.py
What is happening under the hood:
* every SimObject maintains has a ProbeManager.
* during initialization (src/python/m5/simulate.py) first
regProbePoints and
the regProbeListeners is called on each SimObject. this hooks up the
probe
point notify calls with the listeners.
FAQs:
Why did you develop probe points:
* to remove trace, stats gathering, analytical code out of the
functional code.
* the belief that probes could be generically useful.
What is a probe point:
* a probe point is used to notify upon a given event (e.g. cpu commits
an instruction)
What is a probe listener:
* a class that handles whatever the user wishes to do when they are
notified
about an event.
What can be passed on notify:
* probe points are templates, and so the user can generate probes that
pass any
type of argument (by const reference) to a listener.
What relationships can be generated (1:1, 1:N, N:M etc):
* there isn't a restriction. You can hook probe points and listeners up
in a
1:1, 1:N, N:M relationship. They become useful when a number of
modules
listen to the same probe points. The idea being that you can add a
small
number of probes into the source code and develop a larger number of
useful
analysis modules that use information passed by the probes.
Can you give examples:
* adding a probe point to the cpu's commit method allows you to build a
trace
module (outputting assembler), you could re-use this to gather
instruction
distribution (arithmetic, load/store, conditional, control flow)
stats.
Why is the probe interface currently restricted to passing a const
reference:
* the desire, initially at least, is to allow an interface to observe
functionality, but not to change functionality.
* of course this can be subverted by const-casting.
What is the performance impact of adding probes:
* when nothing is actively listening to the probes they should have a
relatively minor impact. Profiling has suggested even with a large
number of
probes (60) the impact of them (when not active) is very minimal
(<1%).
diffstat:
src/cpu/o3/commit.hh | 8 +
src/cpu/o3/commit_impl.hh | 11 +
src/cpu/o3/cpu.cc | 11 +
src/cpu/o3/cpu.hh | 6 +
src/cpu/o3/fetch.hh | 7 +
src/cpu/o3/fetch_impl.hh | 10 +-
src/cpu/o3/iew.hh | 8 +
src/cpu/o3/iew_impl.hh | 11 +
src/cpu/o3/lsq_unit_impl.hh | 2 +
src/cpu/o3/probe/SConscript | 45 ++++++
src/cpu/o3/probe/SimpleTrace.py | 42 +++++
src/cpu/o3/probe/simple_trace.cc | 69 +++++++++
src/cpu/o3/probe/simple_trace.hh | 73 ++++++++++
src/python/m5/SimObject.py | 2 +
src/python/m5/simulate.py | 6 +
src/sim/probe/Probe.py | 47 ++++++
src/sim/probe/SConscript | 44 ++++++
src/sim/probe/probe.cc | 122 +++++++++++++++++
src/sim/probe/probe.hh | 275 +++++++++++++++++++++++++++++++++++++++
src/sim/sim_object.cc | 25 +++-
src/sim/sim_object.hh | 20 ++-
21 files changed, 841 insertions(+), 3 deletions(-)
diffs (truncated from 1127 to 300 lines):
diff -r db307bac42fc -r 91faf6649de0 src/cpu/o3/commit.hh
--- a/src/cpu/o3/commit.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/cpu/o3/commit.hh Fri Jan 24 15:29:30 2014 -0600
@@ -50,6 +50,7 @@
#include "cpu/exetrace.hh"
#include "cpu/inst_seq.hh"
#include "cpu/timebuf.hh"
+#include "sim/probe/probe.hh"
struct DerivO3CPUParams;
@@ -150,6 +151,10 @@
/** Commit policy used in SMT mode. */
CommitPolicy commitPolicy;
+ /** Probe Points. */
+ ProbePointArg<DynInstPtr> *ppCommit;
+ ProbePointArg<DynInstPtr> *ppCommitStall;
+
public:
/** Construct a DefaultCommit with the given parameters. */
DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params);
@@ -160,6 +165,9 @@
/** Registers statistics. */
void regStats();
+ /** Registers probes. */
+ void regProbePoints();
+
/** Sets the list of threads. */
void setThreads(std::vector<Thread *> &threads);
diff -r db307bac42fc -r 91faf6649de0 src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/cpu/o3/commit_impl.hh Fri Jan 24 15:29:30 2014 -0600
@@ -163,6 +163,14 @@
template <class Impl>
void
+DefaultCommit<Impl>::regProbePoints()
+{
+ ppCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Commit");
+ ppCommitStall = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(),
"CommitStall");
+}
+
+template <class Impl>
+void
DefaultCommit<Impl>::regStats()
{
using namespace Stats;
@@ -705,6 +713,8 @@
} else if (!rob->isEmpty(tid)) {
DynInstPtr inst = rob->readHeadInst(tid);
+ ppCommitStall->notify(inst);
+
DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
"%s is head of ROB and not ready\n",
tid, inst->seqNum, inst->pcState());
@@ -1017,6 +1027,7 @@
if (commit_success) {
++num_committed;
+ ppCommit->notify(head_inst);
changedROBNumEntries[tid] = true;
diff -r db307bac42fc -r 91faf6649de0 src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc Fri Jan 24 15:29:30 2014 -0600
+++ b/src/cpu/o3/cpu.cc Fri Jan 24 15:29:30 2014 -0600
@@ -468,6 +468,17 @@
template <class Impl>
void
+FullO3CPU<Impl>::regProbePoints()
+{
+ ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(),
"InstAccessComplete");
+ ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr>
>(getProbeManager(), "DataAccessComplete");
+ fetch.regProbePoints();
+ iew.regProbePoints();
+ commit.regProbePoints();
+}
+
+template <class Impl>
+void
FullO3CPU<Impl>::regStats()
{
BaseO3CPU::regStats();
diff -r db307bac42fc -r 91faf6649de0 src/cpu/o3/cpu.hh
--- a/src/cpu/o3/cpu.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/cpu/o3/cpu.hh Fri Jan 24 15:29:30 2014 -0600
@@ -375,6 +375,12 @@
/** Registers statistics. */
void regStats();
+ ProbePointArg<PacketPtr> *ppInstAccessComplete;
+ ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;
+
+ /** Register probe points. */
+ void regProbePoints();
+
void demapPage(Addr vaddr, uint64_t asn)
{
this->itb->demapPage(vaddr, asn);
diff -r db307bac42fc -r 91faf6649de0 src/cpu/o3/fetch.hh
--- a/src/cpu/o3/fetch.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/cpu/o3/fetch.hh Fri Jan 24 15:29:30 2014 -0600
@@ -55,6 +55,7 @@
#include "mem/packet.hh"
#include "mem/port.hh"
#include "sim/eventq.hh"
+#include "sim/probe/probe.hh"
struct DerivO3CPUParams;
@@ -194,6 +195,9 @@
/** List that has the threads organized by priority. */
std::list<ThreadID> priorityList;
+ /** Probe points. */
+ ProbePointArg<DynInstPtr> *ppFetch;
+
public:
/** DefaultFetch constructor. */
DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params);
@@ -204,6 +208,9 @@
/** Registers statistics. */
void regStats();
+ /** Registers probes. */
+ void regProbePoints();
+
/** Sets the main backwards communication time buffer pointer. */
void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
diff -r db307bac42fc -r 91faf6649de0 src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/cpu/o3/fetch_impl.hh Fri Jan 24 15:29:30 2014 -0600
@@ -163,6 +163,13 @@
template <class Impl>
void
+DefaultFetch<Impl>::regProbePoints()
+{
+ ppFetch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Fetch");
+}
+
+template <class Impl>
+void
DefaultFetch<Impl>::regStats()
{
icacheStallCycles
@@ -401,6 +408,7 @@
}
pkt->req->setAccessLatency();
+ cpu->ppInstAccessComplete->notify(pkt);
// Reset the mem req to NULL.
delete pkt->req;
delete pkt;
@@ -666,7 +674,6 @@
DPRINTF(Fetch, "[tid:%i]: Doing Icache access.\n", tid);
DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
"response.\n", tid);
-
lastIcacheStall[tid] = curTick();
fetchStatus[tid] = IcacheWaitResponse;
}
@@ -1312,6 +1319,7 @@
buildInst(tid, staticInst, curMacroop,
thisPC, nextPC, true);
+ ppFetch->notify(instruction);
numInst++;
#if TRACING_ON
diff -r db307bac42fc -r 91faf6649de0 src/cpu/o3/iew.hh
--- a/src/cpu/o3/iew.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/cpu/o3/iew.hh Fri Jan 24 15:29:30 2014 -0600
@@ -52,6 +52,7 @@
#include "cpu/o3/scoreboard.hh"
#include "cpu/timebuf.hh"
#include "debug/IEW.hh"
+#include "sim/probe/probe.hh"
struct DerivO3CPUParams;
class FUPool;
@@ -122,6 +123,10 @@
/** Writeback status. */
StageStatus wbStatus;
+ /** Probe points. */
+ ProbePointArg<DynInstPtr> *ppMispredict;
+ ProbePointArg<DynInstPtr> *ppDispatch;
+
public:
/** Constructs a DefaultIEW with the given parameters. */
DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params);
@@ -132,6 +137,9 @@
/** Registers statistics. */
void regStats();
+ /** Registers probes. */
+ void regProbePoints();
+
/** Initializes stage; sends back the number of free IQ and LSQ entries. */
void startupStage();
diff -r db307bac42fc -r 91faf6649de0 src/cpu/o3/iew_impl.hh
--- a/src/cpu/o3/iew_impl.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/cpu/o3/iew_impl.hh Fri Jan 24 15:29:30 2014 -0600
@@ -113,6 +113,14 @@
template <class Impl>
void
+DefaultIEW<Impl>::regProbePoints()
+{
+ ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(),
"Dispatch");
+ ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(),
"Mispredict");
+}
+
+template <class Impl>
+void
DefaultIEW<Impl>::regStats()
{
using namespace Stats;
@@ -1158,6 +1166,7 @@
#if TRACING_ON
inst->dispatchTick = curTick() - inst->fetchTick;
#endif
+ ppDispatch->notify(inst);
}
if (!insts_to_dispatch.empty()) {
@@ -1357,6 +1366,8 @@
// If incorrect, then signal the ROB that it must be squashed.
squashDueToBranch(inst, tid);
+ ppMispredict->notify(inst);
+
if (inst->readPredTaken()) {
predictedTakenIncorrect++;
} else {
diff -r db307bac42fc -r 91faf6649de0 src/cpu/o3/lsq_unit_impl.hh
--- a/src/cpu/o3/lsq_unit_impl.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/cpu/o3/lsq_unit_impl.hh Fri Jan 24 15:29:30 2014 -0600
@@ -131,6 +131,8 @@
}
pkt->req->setAccessLatency();
+ cpu->ppDataAccessComplete->notify(std::make_pair(inst, pkt));
+
delete state;
delete pkt->req;
delete pkt;
diff -r db307bac42fc -r 91faf6649de0 src/cpu/o3/probe/SConscript
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/cpu/o3/probe/SConscript Fri Jan 24 15:29:30 2014 -0600
@@ -0,0 +1,45 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Matt Horsnell
+
+Import('*')
+
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