changeset 2a0fbecfeb14 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=2a0fbecfeb14
description:
arch: Make all register index flattening const
This patch makes all the register index flattening methods const for
all the ISAs. As part of this, readMiscRegNoEffect for ARM is also
made const.
diffstat:
src/arch/alpha/isa.hh | 8 ++++----
src/arch/arm/isa.cc | 2 +-
src/arch/arm/isa.hh | 10 +++++-----
src/arch/mips/isa.hh | 8 ++++----
src/arch/power/isa.hh | 8 ++++----
src/arch/sparc/isa.hh | 8 ++++----
src/arch/x86/isa.hh | 8 ++++----
7 files changed, 26 insertions(+), 26 deletions(-)
diffs (228 lines):
diff -r f2ce7114b137 -r 2a0fbecfeb14 src/arch/alpha/isa.hh
--- a/src/arch/alpha/isa.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/arch/alpha/isa.hh Fri Jan 24 15:29:30 2014 -0600
@@ -96,26 +96,26 @@
void unserialize(Checkpoint *cp, const std::string §ion);
int
- flattenIntIndex(int reg)
+ flattenIntIndex(int reg) const
{
return reg;
}
int
- flattenFloatIndex(int reg)
+ flattenFloatIndex(int reg) const
{
return reg;
}
// dummy
int
- flattenCCIndex(int reg)
+ flattenCCIndex(int reg) const
{
return reg;
}
int
- flattenMiscIndex(int reg)
+ flattenMiscIndex(int reg) const
{
return reg;
}
diff -r f2ce7114b137 -r 2a0fbecfeb14 src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc Fri Jan 24 15:29:30 2014 -0600
+++ b/src/arch/arm/isa.cc Fri Jan 24 15:29:30 2014 -0600
@@ -177,7 +177,7 @@
}
MiscReg
-ISA::readMiscRegNoEffect(int misc_reg)
+ISA::readMiscRegNoEffect(int misc_reg) const
{
assert(misc_reg < NumMiscRegs);
diff -r f2ce7114b137 -r 2a0fbecfeb14 src/arch/arm/isa.hh
--- a/src/arch/arm/isa.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/arch/arm/isa.hh Fri Jan 24 15:29:30 2014 -0600
@@ -96,13 +96,13 @@
public:
void clear();
- MiscReg readMiscRegNoEffect(int misc_reg);
+ MiscReg readMiscRegNoEffect(int misc_reg) const;
MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
int
- flattenIntIndex(int reg)
+ flattenIntIndex(int reg) const
{
assert(reg >= 0);
if (reg < NUM_ARCH_INTREGS) {
@@ -135,20 +135,20 @@
}
int
- flattenFloatIndex(int reg)
+ flattenFloatIndex(int reg) const
{
return reg;
}
// dummy
int
- flattenCCIndex(int reg)
+ flattenCCIndex(int reg) const
{
return reg;
}
int
- flattenMiscIndex(int reg)
+ flattenMiscIndex(int reg) const
{
if (reg == MISCREG_SPSR) {
int spsr_idx = NUM_MISCREGS;
diff -r f2ce7114b137 -r 2a0fbecfeb14 src/arch/mips/isa.hh
--- a/src/arch/mips/isa.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/arch/mips/isa.hh Fri Jan 24 15:29:30 2014 -0600
@@ -167,26 +167,26 @@
ISA(Params *p);
int
- flattenIntIndex(int reg)
+ flattenIntIndex(int reg) const
{
return reg;
}
int
- flattenFloatIndex(int reg)
+ flattenFloatIndex(int reg) const
{
return reg;
}
// dummy
int
- flattenCCIndex(int reg)
+ flattenCCIndex(int reg) const
{
return reg;
}
int
- flattenMiscIndex(int reg)
+ flattenMiscIndex(int reg) const
{
return reg;
}
diff -r f2ce7114b137 -r 2a0fbecfeb14 src/arch/power/isa.hh
--- a/src/arch/power/isa.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/arch/power/isa.hh Fri Jan 24 15:29:30 2014 -0600
@@ -87,26 +87,26 @@
}
int
- flattenIntIndex(int reg)
+ flattenIntIndex(int reg) const
{
return reg;
}
int
- flattenFloatIndex(int reg)
+ flattenFloatIndex(int reg) const
{
return reg;
}
// dummy
int
- flattenCCIndex(int reg)
+ flattenCCIndex(int reg) const
{
return reg;
}
int
- flattenMiscIndex(int reg)
+ flattenMiscIndex(int reg) const
{
return reg;
}
diff -r f2ce7114b137 -r 2a0fbecfeb14 src/arch/sparc/isa.hh
--- a/src/arch/sparc/isa.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/arch/sparc/isa.hh Fri Jan 24 15:29:30 2014 -0600
@@ -191,7 +191,7 @@
ThreadContext *tc);
int
- flattenIntIndex(int reg)
+ flattenIntIndex(int reg) const
{
assert(reg < TotalInstIntRegs);
RegIndex flatIndex = intRegMap[reg];
@@ -200,20 +200,20 @@
}
int
- flattenFloatIndex(int reg)
+ flattenFloatIndex(int reg) const
{
return reg;
}
// dummy
int
- flattenCCIndex(int reg)
+ flattenCCIndex(int reg) const
{
return reg;
}
int
- flattenMiscIndex(int reg)
+ flattenMiscIndex(int reg) const
{
return reg;
}
diff -r f2ce7114b137 -r 2a0fbecfeb14 src/arch/x86/isa.hh
--- a/src/arch/x86/isa.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/arch/x86/isa.hh Fri Jan 24 15:29:30 2014 -0600
@@ -70,13 +70,13 @@
void setMiscReg(int miscReg, MiscReg val, ThreadContext *tc);
int
- flattenIntIndex(int reg)
+ flattenIntIndex(int reg) const
{
return reg & ~IntFoldBit;
}
int
- flattenFloatIndex(int reg)
+ flattenFloatIndex(int reg) const
{
if (reg >= NUM_FLOATREGS) {
reg = FLOATREG_STACK(reg - NUM_FLOATREGS,
@@ -86,13 +86,13 @@
}
int
- flattenCCIndex(int reg)
+ flattenCCIndex(int reg) const
{
return reg;
}
int
- flattenMiscIndex(int reg)
+ flattenMiscIndex(int reg) const
{
return reg;
}
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