changeset 21c14a2b2117 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=21c14a2b2117
description:
arch, cpu: Add support for flattening misc register indexes.
With ARMv8 support the same misc register id results in accessing
different
registers depending on the current mode of the processor. This patch
adds
the same orthogonality to the misc register file as the others (int,
float, cc).
For all the othre ISAs this is currently a null-implementation.
Additionally, a system variable is added to all the ISA objects.
diffstat:
src/arch/alpha/AlphaISA.py | 4 ++++
src/arch/alpha/isa.cc | 2 +-
src/arch/alpha/isa.hh | 10 ++++++++++
src/arch/mips/MipsISA.py | 3 +++
src/arch/mips/isa.cc | 3 +--
src/arch/mips/isa.hh | 7 +++++++
src/arch/power/isa.hh | 6 ++++++
src/arch/sparc/isa.hh | 8 +++++++-
src/arch/x86/isa.hh | 6 ++++++
src/cpu/checker/thread_context.hh | 1 +
src/cpu/inorder/thread_context.hh | 3 +++
src/cpu/o3/thread_context.hh | 1 +
src/cpu/o3/thread_context_impl.hh | 7 +++++++
src/cpu/simple_thread.hh | 8 +++++++-
src/cpu/thread_context.hh | 4 ++++
15 files changed, 68 insertions(+), 5 deletions(-)
diffs (264 lines):
diff -r 5a7852a013d4 -r 21c14a2b2117 src/arch/alpha/AlphaISA.py
--- a/src/arch/alpha/AlphaISA.py Fri Jan 24 15:29:30 2014 -0600
+++ b/src/arch/alpha/AlphaISA.py Fri Jan 24 15:29:30 2014 -0600
@@ -35,9 +35,13 @@
#
# Authors: Andreas Sandberg
+from m5.params import *
+from m5.proxy import *
from m5.SimObject import SimObject
class AlphaISA(SimObject):
type = 'AlphaISA'
cxx_class = 'AlphaISA::ISA'
cxx_header = "arch/alpha/isa.hh"
+
+ system = Param.System(Parent.any, "System this ISA object belongs to")
diff -r 5a7852a013d4 -r 21c14a2b2117 src/arch/alpha/isa.cc
--- a/src/arch/alpha/isa.cc Fri Jan 24 15:29:30 2014 -0600
+++ b/src/arch/alpha/isa.cc Fri Jan 24 15:29:30 2014 -0600
@@ -40,7 +40,7 @@
{
ISA::ISA(Params *p)
- : SimObject(p)
+ : SimObject(p), system(p->system)
{
clear();
initializeIprTable();
diff -r 5a7852a013d4 -r 21c14a2b2117 src/arch/alpha/isa.hh
--- a/src/arch/alpha/isa.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/arch/alpha/isa.hh Fri Jan 24 15:29:30 2014 -0600
@@ -39,6 +39,7 @@
#include "arch/alpha/types.hh"
#include "base/types.hh"
#include "sim/sim_object.hh"
+#include "sim/system.hh"
struct AlphaISAParams;
class BaseCPU;
@@ -55,6 +56,9 @@
typedef AlphaISAParams Params;
protected:
+ // Parent system
+ System *system;
+
uint64_t fpcr; // floating point condition codes
uint64_t uniq; // process-unique register
bool lock_flag; // lock flag for LL/SC
@@ -110,6 +114,12 @@
return reg;
}
+ int
+ flattenMiscIndex(int reg)
+ {
+ return reg;
+ }
+
const Params *params() const;
ISA(Params *p);
diff -r 5a7852a013d4 -r 21c14a2b2117 src/arch/mips/MipsISA.py
--- a/src/arch/mips/MipsISA.py Fri Jan 24 15:29:30 2014 -0600
+++ b/src/arch/mips/MipsISA.py Fri Jan 24 15:29:30 2014 -0600
@@ -37,11 +37,14 @@
from m5.SimObject import SimObject
from m5.params import *
+from m5.proxy import *
class MipsISA(SimObject):
type = 'MipsISA'
cxx_class = 'MipsISA::ISA'
cxx_header = "arch/mips/isa.hh"
+ system = Param.System(Parent.any, "System this ISA object belongs to")
+
num_threads = Param.UInt8(1, "Maximum number this ISA can handle")
num_vpes = Param.UInt8(1, "Maximum number of vpes this ISA can handle")
diff -r 5a7852a013d4 -r 21c14a2b2117 src/arch/mips/isa.cc
--- a/src/arch/mips/isa.cc Fri Jan 24 15:29:30 2014 -0600
+++ b/src/arch/mips/isa.cc Fri Jan 24 15:29:30 2014 -0600
@@ -89,8 +89,7 @@
};
ISA::ISA(Params *p)
- : SimObject(p),
- numThreads(p->num_threads), numVpes(p->num_vpes)
+ : SimObject(p), numThreads(p->num_threads), numVpes(p->num_vpes)
{
miscRegFile.resize(NumMiscRegs);
bankType.resize(NumMiscRegs);
diff -r 5a7852a013d4 -r 21c14a2b2117 src/arch/mips/isa.hh
--- a/src/arch/mips/isa.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/arch/mips/isa.hh Fri Jan 24 15:29:30 2014 -0600
@@ -184,6 +184,13 @@
{
return reg;
}
+
+ int
+ flattenMiscIndex(int reg)
+ {
+ return reg;
+ }
+
};
}
diff -r 5a7852a013d4 -r 21c14a2b2117 src/arch/power/isa.hh
--- a/src/arch/power/isa.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/arch/power/isa.hh Fri Jan 24 15:29:30 2014 -0600
@@ -105,6 +105,12 @@
return reg;
}
+ int
+ flattenMiscIndex(int reg)
+ {
+ return reg;
+ }
+
void startup(ThreadContext *tc) {}
/// Explicitly import the otherwise hidden startup
diff -r 5a7852a013d4 -r 21c14a2b2117 src/arch/sparc/isa.hh
--- a/src/arch/sparc/isa.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/arch/sparc/isa.hh Fri Jan 24 15:29:30 2014 -0600
@@ -177,7 +177,6 @@
using SimObject::startup;
protected:
-
bool isHyperPriv() { return hpstate.hpriv; }
bool isPriv() { return hpstate.hpriv || pstate.priv; }
bool isNonPriv() { return !isPriv(); }
@@ -213,6 +212,13 @@
return reg;
}
+ int
+ flattenMiscIndex(int reg)
+ {
+ return reg;
+ }
+
+
typedef SparcISAParams Params;
const Params *params() const;
diff -r 5a7852a013d4 -r 21c14a2b2117 src/arch/x86/isa.hh
--- a/src/arch/x86/isa.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/arch/x86/isa.hh Fri Jan 24 15:29:30 2014 -0600
@@ -91,6 +91,12 @@
return reg;
}
+ int
+ flattenMiscIndex(int reg)
+ {
+ return reg;
+ }
+
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string §ion);
void startup(ThreadContext *tc);
diff -r 5a7852a013d4 -r 21c14a2b2117 src/cpu/checker/thread_context.hh
--- a/src/cpu/checker/thread_context.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/cpu/checker/thread_context.hh Fri Jan 24 15:29:30 2014 -0600
@@ -300,6 +300,7 @@
int flattenIntIndex(int reg) { return actualTC->flattenIntIndex(reg); }
int flattenFloatIndex(int reg) { return actualTC->flattenFloatIndex(reg); }
int flattenCCIndex(int reg) { return actualTC->flattenCCIndex(reg); }
+ int flattenMiscIndex(int reg) { return actualTC->flattenMiscIndex(reg); }
unsigned readStCondFailures()
{ return actualTC->readStCondFailures(); }
diff -r 5a7852a013d4 -r 21c14a2b2117 src/cpu/inorder/thread_context.hh
--- a/src/cpu/inorder/thread_context.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/cpu/inorder/thread_context.hh Fri Jan 24 15:29:30 2014 -0600
@@ -273,6 +273,9 @@
int flattenCCIndex(int reg)
{ return cpu->isa[thread->threadId()]->flattenCCIndex(reg); }
+ int flattenMiscIndex(int reg)
+ { return cpu->isa[thread->threadId()]->flattenMiscIndex(reg); }
+
void activateContext(Cycles delay)
{ cpu->activateContext(thread->threadId(), delay); }
diff -r 5a7852a013d4 -r 21c14a2b2117 src/cpu/o3/thread_context.hh
--- a/src/cpu/o3/thread_context.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/cpu/o3/thread_context.hh Fri Jan 24 15:29:30 2014 -0600
@@ -244,6 +244,7 @@
virtual int flattenIntIndex(int reg);
virtual int flattenFloatIndex(int reg);
virtual int flattenCCIndex(int reg);
+ virtual int flattenMiscIndex(int reg);
/** Returns the number of consecutive store conditional failures. */
// @todo: Figure out where these store cond failures should go.
diff -r 5a7852a013d4 -r 21c14a2b2117 src/cpu/o3/thread_context_impl.hh
--- a/src/cpu/o3/thread_context_impl.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/cpu/o3/thread_context_impl.hh Fri Jan 24 15:29:30 2014 -0600
@@ -292,6 +292,13 @@
}
template <class Impl>
+int
+O3ThreadContext<Impl>::flattenMiscIndex(int reg)
+{
+ return cpu->isa[thread->threadId()]->flattenMiscIndex(reg);
+}
+
+template <class Impl>
void
O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
{
diff -r 5a7852a013d4 -r 21c14a2b2117 src/cpu/simple_thread.hh
--- a/src/cpu/simple_thread.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/cpu/simple_thread.hh Fri Jan 24 15:29:30 2014 -0600
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011 ARM Limited
+ * Copyright (c) 2011-2012 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -415,6 +415,12 @@
return isa->flattenCCIndex(reg);
}
+ int
+ flattenMiscIndex(int reg)
+ {
+ return isa->flattenMiscIndex(reg);
+ }
+
unsigned readStCondFailures() { return storeCondFailures; }
void setStCondFailures(unsigned sc_failures)
diff -r 5a7852a013d4 -r 21c14a2b2117 src/cpu/thread_context.hh
--- a/src/cpu/thread_context.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/cpu/thread_context.hh Fri Jan 24 15:29:30 2014 -0600
@@ -235,6 +235,7 @@
virtual int flattenIntIndex(int reg) = 0;
virtual int flattenFloatIndex(int reg) = 0;
virtual int flattenCCIndex(int reg) = 0;
+ virtual int flattenMiscIndex(int reg) = 0;
virtual uint64_t
readRegOtherThread(int misc_reg, ThreadID tid)
@@ -451,6 +452,9 @@
int flattenCCIndex(int reg)
{ return actualTC->flattenCCIndex(reg); }
+ int flattenMiscIndex(int reg)
+ { return actualTC->flattenMiscIndex(reg); }
+
unsigned readStCondFailures()
{ return actualTC->readStCondFailures(); }
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