Hi Nilay, You have to apply: http://reviews.gem5.org/r/2153/
then: http://reviews.gem5.org/r/2039/ The busses are doing what they should. The bridge is responsible for storing the src. Hence the need for the bridges between the RubyPort and the bus. The RubyPort is currently an under-cover bus :-). Andreas On 30/01/2014 18:35, "Nilay Vaish" <[email protected]> wrote: >On Thu, 30 Jan 2014, Nilay Vaish wrote: > >> On Tue, 21 Jan 2014, Andreas Hansson wrote: >> >>> >>> >>> > On Jan. 20, 2014, 9:02 p.m., Nilay Vaish wrote: >>> > > src/mem/ruby/system/RubyPort.cc, line 164 >>> > > >>><http://reviews.gem5.org/r/2039/diff/1/?file=37873#file37873line164> >>> > > >>> > > How do you know that the destination value is what it should >>>be? >>> > > Should not >>> > > the packet be routed using the address in the packet? >>> >>> Responses should be routed on the dest field in the classic memory >>>system. >>> Any multiplexing component is responsible for setting the source when >>>the >>> request passes through. Only requests are routed based on address. >>> >>> Moreover, any component that changes the src has to store the old >>>value in >>> a sender state and restore it later. >> >> Yes, and I don't think noncoherent_bus.cc is doing what you wrote. It >>simply >> overwrites the source that was stored in the packet through the >> aforementioned line in RubyPort.cc. It seems the patch is working only >> because each ruby port has only one master port connected to the piobus. >> > >Andreas, test the long ruby fs regression with rb2039 and the following >patch applied. It should fail (it did when I tested) as the noncoherent >bus does not store the source port id. > >-- >Nilay > >diff -r 219dd4519afc -r 34547a0b92c4 >tests/configs/pc-simple-timing-ruby.py >--- a/tests/configs/pc-simple-timing-ruby.py Wed Jan 29 23:33:08 2014 >-0600 >+++ b/tests/configs/pc-simple-timing-ruby.py Thu Jan 30 12:20:06 2014 >-0600 >@@ -68,6 +68,13 @@ > system.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = >system.cpu_clk_domain) > for i in xrange(options.num_cpus)] > >+for (i, cpu) in enumerate(system.cpu): >+ # create the interrupt controller >+ cpu.createInterruptController() >+ cpu.interrupts.pio = system.piobus.master >+ cpu.interrupts.int_master = system.piobus.slave >+ cpu.interrupts.int_slave = system.piobus.master >+ > Ruby.create_system(options, system, system.piobus, system._dma_ports) > > # Create a seperate clock domain for Ruby >@@ -75,16 +82,11 @@ > voltage_domain = >system.voltage_domain) > > for (i, cpu) in enumerate(system.cpu): >- # create the interrupt controller >- cpu.createInterruptController() > # Tie the cpu ports to the correct ruby system ports > cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave > cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave > cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave > cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave >- cpu.interrupts.pio = system.piobus.master >- cpu.interrupts.int_master = system.piobus.slave >- cpu.interrupts.int_slave = system.piobus.master > > # Set access_phys_mem to True for ruby port > system.ruby._cpu_ruby_ports[i].access_phys_mem = True > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782 _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
