changeset c0db268f811b in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c0db268f811b
description:
ruby: correct errors in changeset 4eec7bdde5b0
Couple of errors were discovered in 4eec7bdde5b0 which necessitated
this patch.
Firstly, we create interrupt controllers in the se mode, but no piobus
was
being created. RubyPort, which earlier used to ignore range changes now
forwards those to the piobus. The lack of piobus resulted in
segmentation
fault. This patch creates a piobus even in se mode. It is not created
only
when some tester is running. Secondly, I had missed out on modifying
port
connections for other coherence protocols.
diffstat:
configs/example/se.py | 5 +++--
configs/ruby/MESI_Three_Level.py | 4 +++-
configs/ruby/MI_example.py | 4 +++-
configs/ruby/MOESI_CMP_directory.py | 4 +++-
configs/ruby/MOESI_CMP_token.py | 4 +++-
configs/ruby/MOESI_hammer.py | 4 +++-
tests/configs/simple-timing-ruby.py | 4 ++--
7 files changed, 20 insertions(+), 9 deletions(-)
diffs (100 lines):
diff -r d76312a74915 -r c0db268f811b configs/example/se.py
--- a/configs/example/se.py Sun Feb 23 19:16:16 2014 -0600
+++ b/configs/example/se.py Mon Feb 24 20:50:05 2014 -0600
@@ -231,9 +231,10 @@
# Set the option for physmem so that it is not allocated any space
system.physmem = MemClass(range=AddrRange(options.mem_size),
null = True)
+ options.use_map = True
- options.use_map = True
- Ruby.create_system(options, system)
+ system.piobus = NoncoherentBus()
+ Ruby.create_system(options, system, system.piobus)
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
for i in xrange(np):
diff -r d76312a74915 -r c0db268f811b configs/ruby/MESI_Three_Level.py
--- a/configs/ruby/MESI_Three_Level.py Sun Feb 23 19:16:16 2014 -0600
+++ b/configs/ruby/MESI_Three_Level.py Mon Feb 24 20:50:05 2014 -0600
@@ -117,7 +117,9 @@
cluster_id = i, ruby_system = ruby_system)
if piobus != None:
- cpu_seq.pio_port = piobus.slave
+ cpu_seq.pio_master_port = piobus.slave
+ cpu_seq.mem_master_port = piobus.slave
+ cpu_seq.pio_slave_port = piobus.master
exec("ruby_system.l0_cntrl%d = l0_cntrl" % (
i*num_cpus_per_cluster+j))
diff -r d76312a74915 -r c0db268f811b configs/ruby/MI_example.py
--- a/configs/ruby/MI_example.py Sun Feb 23 19:16:16 2014 -0600
+++ b/configs/ruby/MI_example.py Mon Feb 24 20:50:05 2014 -0600
@@ -92,7 +92,9 @@
l1_cntrl.sequencer = cpu_seq
if piobus != None:
- cpu_seq.pio_port = piobus.slave
+ cpu_seq.pio_master_port = piobus.slave
+ cpu_seq.mem_master_port = piobus.slave
+ cpu_seq.pio_slave_port = piobus.master
exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
#
diff -r d76312a74915 -r c0db268f811b configs/ruby/MOESI_CMP_directory.py
--- a/configs/ruby/MOESI_CMP_directory.py Sun Feb 23 19:16:16 2014 -0600
+++ b/configs/ruby/MOESI_CMP_directory.py Mon Feb 24 20:50:05 2014 -0600
@@ -102,7 +102,9 @@
l1_cntrl.sequencer = cpu_seq
if piobus != None:
- cpu_seq.pio_port = piobus.slave
+ cpu_seq.pio_master_port = piobus.slave
+ cpu_seq.mem_master_port = piobus.slave
+ cpu_seq.pio_slave_port = piobus.master
exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
#
diff -r d76312a74915 -r c0db268f811b configs/ruby/MOESI_CMP_token.py
--- a/configs/ruby/MOESI_CMP_token.py Sun Feb 23 19:16:16 2014 -0600
+++ b/configs/ruby/MOESI_CMP_token.py Mon Feb 24 20:50:05 2014 -0600
@@ -122,7 +122,9 @@
l1_cntrl.sequencer = cpu_seq
if piobus != None:
- cpu_seq.pio_port = piobus.slave
+ cpu_seq.pio_master_port = piobus.slave
+ cpu_seq.mem_master_port = piobus.slave
+ cpu_seq.pio_slave_port = piobus.master
exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
#
diff -r d76312a74915 -r c0db268f811b configs/ruby/MOESI_hammer.py
--- a/configs/ruby/MOESI_hammer.py Sun Feb 23 19:16:16 2014 -0600
+++ b/configs/ruby/MOESI_hammer.py Mon Feb 24 20:50:05 2014 -0600
@@ -115,7 +115,9 @@
l1_cntrl.sequencer = cpu_seq
if piobus != None:
- cpu_seq.pio_port = piobus.slave
+ cpu_seq.pio_master_port = piobus.slave
+ cpu_seq.mem_master_port = piobus.slave
+ cpu_seq.pio_slave_port = piobus.master
if options.recycle_latency:
l1_cntrl.recycle_latency = options.recycle_latency
diff -r d76312a74915 -r c0db268f811b tests/configs/simple-timing-ruby.py
--- a/tests/configs/simple-timing-ruby.py Sun Feb 23 19:16:16 2014 -0600
+++ b/tests/configs/simple-timing-ruby.py Mon Feb 24 20:50:05 2014 -0600
@@ -79,8 +79,8 @@
voltage_domain = system.voltage_domain)
system.mem_ranges = AddrRange('256MB')
-
-Ruby.create_system(options, system)
+system.piobus = NoncoherentBus()
+Ruby.create_system(options, system, system.piobus)
# Create a separate clock for Ruby
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
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