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Ship it! Ship It! - Nilay Vaish On Feb. 22, 2014, 3:33 p.m., Anthony Gutierrez wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2173/ > ----------------------------------------------------------- > > (Updated Feb. 22, 2014, 3:33 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10084:7ef68365149e > --------------------------- > arm: make the RandomRepl tags the default for the O3_ARM_v7aL2 > > > the Cortex-A15 has a random replacement policy for its L2 cache. see the > Cortex-A15 Technical Reference Manual 7.1 About the L2 memory system. this > patch makes the RandomRepl tags the default for the ARM O3 CPU's L2 cache. > > > Diffs > ----- > > configs/common/O3_ARM_v7a.py 2beea2a439b43bf95bc040198322d4869b07f4f3 > > Diff: http://reviews.gem5.org/r/2173/diff/ > > > Testing > ------- > > Used the memory latency benchmark from LMBench to evaluate the accuracy of > gem5's memory system vs. a VExpress board, with this patch the accuracy is > much improved. See figure 4a. here: > > http://web.eecs.umich.edu/~atgutier/papers/ispass_2014.pdf > > > Thanks, > > Anthony Gutierrez > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
