> On Feb. 23, 2014, 5:23 p.m., Steve Reinhardt wrote: > > Does LL put the core to sleep in ARM? For Alpha, where LLSC was originally > > implemented, these were two separate things (LL/SC vs. ARM/QUIESCE). While > > x86 doesn't have LL/SC, we do have ARM/QUIESCE in the form of > > MONITOR/MWAIT. Which makes me wonder whether MONITOR/MWAIT would work on a > > system with no caches... > > > > Also, realizing that Alpha almost had an ARM instruction, makes me wonder > > if you might add an ALPHA instruction someday just to reciprocate... > > Andreas Hansson wrote: > The OS uses the Wait For Event (WFE) mechanism to conserve energy, and an > access to any locked address has to wake the core up. > > Andreas Hansson wrote: > Good to go?
Sorry, got distracted ;). So does that mean in ARM that an LL also effectively acts as an x86 MONITOR? I'm just trying to map the ARM behavior (ahem, "behaviour") to my understanding of Alpha & x86, to see if this is an ARM-specific thing, and if there's a similar issue for other ISAs. At the very worst I might ask you to tweak the comment a little to expand your explanation of the scenario--since Alpha doesn't sleep on LLSC, as it stands it's a little confusing if that's all you're familiar with--but other than that the code is fine. - Steve ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2163/#review4912 ----------------------------------------------------------- On Feb. 21, 2014, 5:21 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2163/ > ----------------------------------------------------------- > > (Updated Feb. 21, 2014, 5:21 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10074:2b52a708bc9a > --------------------------- > mem: Wakeup sleeping CPUs without caches on LLSC > > For systems without caches, the LLSC code does not get snoops for > wake-ups. We add the LLSC code in the abstract memory to do the job > for us. > > > Diffs > ----- > > src/arch/null/cpu_dummy.hh 2360411a16be > src/mem/abstract_mem.cc 2360411a16be > > Diff: http://reviews.gem5.org/r/2163/diff/ > > > Testing > ------- > > All regressions pass. Previously stalling multi-core boot now proceeds. > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
