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Ship it! Ship It! - Steve Reinhardt On March 6, 2014, 7:24 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2163/ > ----------------------------------------------------------- > > (Updated March 6, 2014, 7:24 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10101:d470799261e2 > --------------------------- > mem: Wakeup sleeping CPUs without caches on LLSC > > For systems without caches, the LLSC code does not get snoops for > wake-ups. We add the LLSC code in the abstract memory to do the job > for us. > > > Diffs > ----- > > src/arch/null/cpu_dummy.hh 24cfe67c0749 > src/mem/abstract_mem.cc 24cfe67c0749 > > Diff: http://reviews.gem5.org/r/2163/diff/ > > > Testing > ------- > > All regressions pass. Previously stalling multi-core boot now proceeds. > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
