changeset b5de69974a2e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b5de69974a2e
description:
mem: Wakeup sleeping CPUs without caches on LLSC
For systems without caches, the LLSC code does not get snoops for
wake-ups. We add the LLSC code in the abstract memory to do the job
for us.
diffstat:
src/arch/null/cpu_dummy.hh | 1 +
src/mem/abstract_mem.cc | 8 ++++++++
2 files changed, 9 insertions(+), 0 deletions(-)
diffs (36 lines):
diff -r 39d9d14d084f -r b5de69974a2e src/arch/null/cpu_dummy.hh
--- a/src/arch/null/cpu_dummy.hh Thu Mar 06 15:59:53 2014 +0100
+++ b/src/arch/null/cpu_dummy.hh Fri Mar 07 15:56:23 2014 -0500
@@ -47,6 +47,7 @@
public:
static int numSimulatedInsts() { return 0; }
static int numSimulatedOps() { return 0; }
+ static void wakeup() { ; }
};
#endif // __ARCH_NULL_CPU_DUMMY_HH__
diff -r 39d9d14d084f -r b5de69974a2e src/mem/abstract_mem.cc
--- a/src/mem/abstract_mem.cc Thu Mar 06 15:59:53 2014 +0100
+++ b/src/mem/abstract_mem.cc Fri Mar 07 15:56:23 2014 -0500
@@ -44,6 +44,8 @@
#include "arch/registers.hh"
#include "config/the_isa.hh"
+#include "cpu/base.hh"
+#include "cpu/thread_context.hh"
#include "debug/LLSC.hh"
#include "debug/MemoryAccess.hh"
#include "mem/abstract_mem.hh"
@@ -260,6 +262,12 @@
if (i->addr == paddr) {
DPRINTF(LLSC, "Erasing lock record: context %d addr %#x\n",
i->contextId, paddr);
+ // For ARM, a spinlock would typically include a Wait
+ // For Event (WFE) to conserve energy. The ARMv8
+ // architecture specifies that an event is
+ // automatically generated when clearing the exclusive
+ // monitor to wake up the processor in WFE.
+
system()->getThreadContext(i->contextId)->getCpuPtr()->wakeup();
i = lockedAddrList.erase(i);
} else {
i++;
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