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Ship it! I realise it is beyond this patch, but it would be very nice to see the memory controller broken out of Ruby. In other words, keep the directory controller, and use a "normal" gem5 port to interface to a subclass of AbstractMemory. tests/configs/pc-simple-timing-ruby.py <http://reviews.gem5.org/r/2209/#comment4586> Why is this needed? - Andreas Hansson On March 12, 2014, 6:55 p.m., Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2209/ > ----------------------------------------------------------- > > (Updated March 12, 2014, 6:55 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10118:0d63c197096d > --------------------------- > ruby: no functional physical memory > This patch removes the functional copy of memory that was in place for > ruby fs simulations. All the memory accesses now source and sink values > to the memory maintained by ruby. > > > Diffs > ----- > > configs/example/fs.py fd90d9e55e5c > configs/ruby/MESI_Two_Level.py fd90d9e55e5c > configs/ruby/Ruby.py fd90d9e55e5c > src/mem/protocol/MESI_Two_Level-dma.sm fd90d9e55e5c > src/mem/protocol/MOESI_CMP_directory-dma.sm fd90d9e55e5c > src/mem/protocol/MOESI_CMP_token-dma.sm fd90d9e55e5c > src/mem/ruby/system/DMASequencer.hh fd90d9e55e5c > src/mem/ruby/system/DMASequencer.cc fd90d9e55e5c > src/mem/ruby/system/RubyPort.hh fd90d9e55e5c > src/mem/ruby/system/RubyPort.cc fd90d9e55e5c > src/mem/ruby/system/Sequencer.py fd90d9e55e5c > tests/configs/pc-simple-timing-ruby.py fd90d9e55e5c > > Diff: http://reviews.gem5.org/r/2209/diff/ > > > Testing > ------- > > > Thanks, > > Nilay Vaish > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
