I get 5 100-million-instruction simpoints for each benchmark in SPEC CPU 2006 with *ref input*. I am using cross-tool arm-cortex_a15-linux-gnueabi-gcc version 4.8.2 to compile.
For gcc, I got from 0.2% to 5% miss rate from tournament, but 3% to 22% miss rate from bi-mode cross all simpoints. Most weird part is hmmer, I got from 0.3% to 0.5% miss rate from tournament, but 52% to 60% miss rate from bi-mode. -- Best Regards Yan Zi On 2 Jul 2014, at 17:11, Anthony Gutierrez via gem5-dev wrote: > This could depend on a lot of factors. How are you running the benchmarks? > > E.g., running SPEC 2k6's gcc to completion with the train input set in FS > mode yields a 6.45% miss rate for bi-mode, while the tournament predictor > yields a 7.12% miss rate. > > > Anthony Gutierrez > http://web.eecs.umich.edu/~atgutier > > > On Wed, Jul 2, 2014 at 4:37 PM, Zi Yan via gem5-dev <[email protected]> > wrote: > >> Hi, >> >> I just updated gem5-dev and got bi-mode as ARM's default >> branch predictor. >> >> I got mis-prediction rate >> (system.cpu.branchPred.condIncorrect/system.cpu.branchPred.condPredicted) >> ranging from 10% to 60%, whereas I saw mis-prediction rate ranging >> from 1% to 9% with tournament for SPEC CPU 2006 benchmarks. >> >> Should I expect this from bi-mode? >> >> Thanks. >> >> -- >> Best Regards >> Yan Zi >> _______________________________________________ >> gem5-dev mailing list >> [email protected] >> http://m5sim.org/mailman/listinfo/gem5-dev >> > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
