----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2332/#review5272 -----------------------------------------------------------
I'll take Mitch and Stephen's word that we need this patch. I'll still like to understand it in more detail before we commit it. src/cpu/o3/inst_queue.hh <http://reviews.gem5.org/r/2332/#comment4801> I think we need better differentiation between this list and the one declared after it. On further reading, it seems that we may not need the two lists. Can we just mark the instructions that they should be retried? While adding them back to the ready queue, we can check which ones are marked. Or may be keep an iterator that tracks the point till which we should retry. One more thought, can we do with a queue instead of a list? src/cpu/o3/inst_queue_impl.hh <http://reviews.gem5.org/r/2332/#comment4802> Should we not clear retryMemInsts as well? src/cpu/o3/inst_queue_impl.hh <http://reviews.gem5.org/r/2332/#comment4803> Let's retain the new line above this while loop. src/cpu/o3/inst_queue_impl.hh <http://reviews.gem5.org/r/2332/#comment4804> We should use nullptr now that we have gcc minimum dependency at 4.6. src/cpu/o3/lsq_unit.hh <http://reviews.gem5.org/r/2332/#comment4805> Do we need all these changes that appear over next 15-20 lines? It seems from my initial reading that the previous code structure could have been retained. src/cpu/o3/lsq_unit_impl.hh <http://reviews.gem5.org/r/2332/#comment4806> New line after. - Nilay Vaish On Aug. 13, 2014, 2:06 p.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2332/ > ----------------------------------------------------------- > > (Updated Aug. 13, 2014, 2:06 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10300:bddebc19285f > --------------------------- > cpu: Fix cached block load behavior in o3 cpu > > This patch fixes the load blocked/replay mechanism in the o3 cpu. Rather than > flushing the entire pipeline, this patch replays loads once the cache becomes > unblocked. > > Additionally, deferred memory instructions (loads which had conflicting > stores), > when replayed would not respect the number of functional units (only respected > issue width). This patch also corrects that. > > Improvements over 20% have been observed on a microbenchmark designed to > exercise this behavior. > > > Diffs > ----- > > src/cpu/o3/iew.hh 79fde1c67ed8 > src/cpu/o3/iew_impl.hh 79fde1c67ed8 > src/cpu/o3/inst_queue.hh 79fde1c67ed8 > src/cpu/o3/inst_queue_impl.hh 79fde1c67ed8 > src/cpu/o3/lsq.hh 79fde1c67ed8 > src/cpu/o3/lsq_impl.hh 79fde1c67ed8 > src/cpu/o3/lsq_unit.hh 79fde1c67ed8 > src/cpu/o3/lsq_unit_impl.hh 79fde1c67ed8 > src/cpu/o3/mem_dep_unit.hh 79fde1c67ed8 > src/cpu/o3/mem_dep_unit_impl.hh 79fde1c67ed8 > > Diff: http://reviews.gem5.org/r/2332/diff/ > > > Testing > ------- > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
