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(Updated Aug. 27, 2014, 4:13 p.m.) Review request for Default. Summary (updated) ----------------- cpu: Fix cache blocked load behavior in o3 cpu Repository: gem5 Description (updated) ------- Changeset 10312:1529a4fc718f --------------------------- cpu: Fix cache blocked load behavior in o3 cpu This patch fixes the load blocked/replay mechanism in the o3 cpu. Rather than flushing the entire pipeline, this patch replays loads once the cache becomes unblocked. Additionally, deferred memory instructions (loads which had conflicting stores), when replayed would not respect the number of functional units (only respected issue width). This patch also corrects that. Improvements over 20% have been observed on a microbenchmark designed to exercise this behavior. Diffs (updated) ----- src/cpu/o3/iew.hh 2a1d75864ad2 src/cpu/o3/iew_impl.hh 2a1d75864ad2 src/cpu/o3/inst_queue.hh 2a1d75864ad2 src/cpu/o3/inst_queue_impl.hh 2a1d75864ad2 src/cpu/o3/lsq.hh 2a1d75864ad2 src/cpu/o3/lsq_impl.hh 2a1d75864ad2 src/cpu/o3/lsq_unit.hh 2a1d75864ad2 src/cpu/o3/lsq_unit_impl.hh 2a1d75864ad2 src/cpu/o3/mem_dep_unit.hh 2a1d75864ad2 src/cpu/o3/mem_dep_unit_impl.hh 2a1d75864ad2 Diff: http://reviews.gem5.org/r/2332/diff/ Testing ------- Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
