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Ship it! Ship It! - Andreas Sandberg On Aug. 25, 2014, 10:10 p.m., Alexandru Dutu wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2319/ > ----------------------------------------------------------- > > (Updated Aug. 25, 2014, 10:10 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10265:d518cde600e0 > --------------------------- > Mem: adding architectural page table support for SE mode > This patch enables the use of page tables that are stored in system memory > and respect x86 specification, in SE mode. It defines an architectural > page table for x86 as a MultiLevelPageTable class and puts a placeholder > class for other ISAs page tables, giving the possibility for future > implementation. > > > Diffs > ----- > > src/arch/alpha/process.hh c00b5ba43967e7e48a28b7ddc48c9f4afaf2ab76 > src/arch/arm/process.hh c00b5ba43967e7e48a28b7ddc48c9f4afaf2ab76 > src/arch/mips/process.hh c00b5ba43967e7e48a28b7ddc48c9f4afaf2ab76 > src/arch/power/process.hh c00b5ba43967e7e48a28b7ddc48c9f4afaf2ab76 > src/arch/sparc/process.hh c00b5ba43967e7e48a28b7ddc48c9f4afaf2ab76 > src/arch/x86/pagetable.hh c00b5ba43967e7e48a28b7ddc48c9f4afaf2ab76 > src/arch/x86/pagetable_walker.cc c00b5ba43967e7e48a28b7ddc48c9f4afaf2ab76 > src/arch/x86/process.hh c00b5ba43967e7e48a28b7ddc48c9f4afaf2ab76 > src/arch/x86/system.hh c00b5ba43967e7e48a28b7ddc48c9f4afaf2ab76 > src/mem/SConscript c00b5ba43967e7e48a28b7ddc48c9f4afaf2ab76 > src/sim/Process.py c00b5ba43967e7e48a28b7ddc48c9f4afaf2ab76 > src/sim/process.hh c00b5ba43967e7e48a28b7ddc48c9f4afaf2ab76 > src/sim/process.cc c00b5ba43967e7e48a28b7ddc48c9f4afaf2ab76 > > Diff: http://reviews.gem5.org/r/2319/diff/ > > > Testing > ------- > > Regressions passed. > > > Thanks, > > Alexandru Dutu > > _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
