changeset 77af86f37337 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=77af86f37337
description:
mem: adding a multi-level page table class
This patch defines a multi-level page table class that stores the page
table in
system memory, consistent with ISA specifications. In this way, cpu
models that
use the actual hardware to execute (e.g. KvmCPU), are able to traverse
the page
table.
diffstat:
src/mem/multi_level_page_table.cc | 33 +++
src/mem/multi_level_page_table.hh | 157 ++++++++++++++++
src/mem/multi_level_page_table_impl.hh | 312 +++++++++++++++++++++++++++++++++
src/mem/page_table.cc | 34 +--
src/mem/page_table.hh | 100 ++++++++-
src/mem/se_translating_port_proxy.hh | 2 +-
src/sim/process.cc | 6 +-
src/sim/process.hh | 3 +-
8 files changed, 610 insertions(+), 37 deletions(-)
diffs (truncated from 870 to 300 lines):
diff -r 2a1d75864ad2 -r 77af86f37337 src/mem/multi_level_page_table.cc
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/mem/multi_level_page_table.cc Tue Apr 01 12:18:12 2014 -0500
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Alexandru Dutu
+ */
+
+#include "mem/multi_level_page_table_impl.hh"
+
+template class MultiLevelPageTable<TheISA::PageTableOps>;
diff -r 2a1d75864ad2 -r 77af86f37337 src/mem/multi_level_page_table.hh
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/mem/multi_level_page_table.hh Tue Apr 01 12:18:12 2014 -0500
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Alexandru Dutu
+ */
+
+/**
+ * @file
+ * Declaration of a multi-level page table.
+ */
+
+#ifndef __MEM_MULTI_LEVEL_PAGE_TABLE_HH__
+#define __MEM_MULTI_LEVEL_PAGE_TABLE_HH__
+
+#include <string>
+
+#include "arch/isa_traits.hh"
+#include "arch/tlb.hh"
+#include "base/types.hh"
+#include "config/the_isa.hh"
+#include "mem/page_table.hh"
+#include "sim/serialize.hh"
+#include "sim/system.hh"
+
+/**
+ * This class implements an in-memory multi-level page table that can be
+ * configured to follow ISA specifications. It can be used instead of the
+ * PageTable class in SE mode to allow CPU models (e.g. X86KvmCPU)
+ * to do a normal page table walk.
+ *
+ * To reduce memory required to store the page table, a multi-level page
+ * table stores its translations similarly with a radix tree. Let n be
+ * the number of levels and {Ln, Ln-1, ..., L1, L0} a set that specifies
+ * the number of entries for each level as base 2 logarithm values. A
+ * multi-level page table will store its translations at level 0 (the
+ * leaves of the tree) and it will be layed out in memory in the
+ * following way:
+ *
+ * +------------------------------+
+ * level n |Ln-1_E0|Ln-1_E1|...|Ln-1_E2^Ln|
+ * +------------------------------+
+ * / \
+ * +------------------------+ +------------------------+
+ * level n-1 |Ln-2_E0|...|Ln-2_E2^Ln-1| |Ln-2_E0|...|Ln-2_E2^Ln-1|
+ * +------------------------+ +------------------------+
+ * / \ / \
+ * .
+ * .
+ * .
+ * / / \
+ * +------------------+ +------------+ +------------+
+ * level 1 |L0_E1|...|L0_E2^L1| |...|L0_E2^L1| ... |...|L0_E2^L1|
+ * +------------------+ +------------+ +------------+
+ * , where
+ * +------------------------------+
+ * |Lk-1_E0|Lk-1_E1|...|Lk-1_E2^Lk|
+ * +------------------------------+
+ * is a level k entry that holds 2^Lk entries in Lk-1 level.
+ *
+ * Essentially, a level n entry will contain 2^Ln level n-1 entries,
+ * a level n-1 entry will hold 2^Ln-1 level n-2 entries etc.
+ *
+ * The virtual address is split into offsets that index into the
+ * different levels of the page table.
+ *
+ * +--------------------------------+
+ * |LnOffset|...|L1Offset|PageOffset|
+ * +--------------------------------+
+ *
+ * For example L0Offset will be formed by the bits in range
+ * [log2(PageOffset), log2(PageOffset)+L0].
+ *
+ * For every level of the page table, from n to 1, the base address
+ * of the entry is loaded, the offset in the virtual address for
+ * that particular level is used to index into the entry which
+ * will reveal the memory address of the entry in the next level.
+ *
+ * @see MultiLevelPageTable
+ */
+template <class ISAOps>
+class MultiLevelPageTable : public PageTableBase
+{
+ /**
+ * ISA specific operations
+ */
+ ISAOps pTableISAOps;
+
+ /**
+ * Pointer to System object
+ */
+ System *system;
+
+ /**
+ * Physical address to the last level of the page table
+ */
+ Addr basePtr;
+
+ /**
+ * Vector with sizes of all levels in base 2 logarithmic
+ */
+ const std::vector<uint8_t> logLevelSize;
+
+ /**
+ * Number of levels contained by the page table
+ */
+ const uint64_t numLevels;
+
+ /**
+ * Method for walking the page table
+ *
+ * @param vaddr Virtual address that is being looked-up
+ * @param allocate Specifies whether memory should be allocated while
+ * walking the page table
+ * @return PTE_addr The address of the found PTE
+ * @retval true if the page table walk has succeded, false otherwhise
+ */
+ bool walk(Addr vaddr, bool allocate, Addr &PTE_addr);
+
+public:
+ MultiLevelPageTable(const std::string &__name, uint64_t _pid, System
*_sys);
+ ~MultiLevelPageTable();
+
+ void initState(ThreadContext* tc);
+
+ void map(Addr vaddr, Addr paddr, int64_t size, bool clobber = false);
+ void remap(Addr vaddr, int64_t size, Addr new_vaddr);
+ void unmap(Addr vaddr, int64_t size);
+ bool isUnmapped(Addr vaddr, int64_t size);
+ bool lookup(Addr vaddr, TheISA::TlbEntry &entry);
+ void serialize(std::ostream &os);
+ void unserialize(Checkpoint *cp, const std::string §ion);
+};
+#endif // __MEM_MULTI_LEVEL_PAGE_TABLE_HH__
diff -r 2a1d75864ad2 -r 77af86f37337 src/mem/multi_level_page_table_impl.hh
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/mem/multi_level_page_table_impl.hh Tue Apr 01 12:18:12 2014 -0500
@@ -0,0 +1,312 @@
+/*
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Alexandru Dutu
+ */
+
+/**
+ * @file
+ * Definitions of page table
+ */
+#include <fstream>
+#include <map>
+#include <string>
+
+#include "base/bitfield.hh"
+#include "base/intmath.hh"
+#include "base/trace.hh"
+#include "config/the_isa.hh"
+#include "debug/MMU.hh"
+#include "mem/multi_level_page_table.hh"
+#include "sim/faults.hh"
+#include "sim/sim_object.hh"
+
+using namespace std;
+using namespace TheISA;
+
+template <class ISAOps>
+MultiLevelPageTable<ISAOps>::MultiLevelPageTable(const std::string &__name,
uint64_t _pid, System *_sys)
+ : PageTableBase(__name, _pid), system(_sys),
+ logLevelSize(PageTableLayout),
+ numLevels(logLevelSize.size())
+{
+}
+
+template <class ISAOps>
+MultiLevelPageTable<ISAOps>::~MultiLevelPageTable()
+{
+}
+
+template <class ISAOps>
+void
+MultiLevelPageTable<ISAOps>::initState(ThreadContext* tc)
+{
+ basePtr = pTableISAOps.getBasePtr(tc);
+ if (basePtr == 0) basePtr++;
+ DPRINTF(MMU, "basePtr: %d\n", basePtr);
+
+ system->pagePtr = basePtr;
+
+ /* setting first level of the page table */
+ uint64_t log_req_size = floorLog2(sizeof(PageTableEntry)) +
+ logLevelSize[numLevels-1];
+ assert(log_req_size >= LogVMPageSize);
+ uint64_t npages = 1 << (log_req_size - LogVMPageSize);
+
+ Addr paddr = system->allocPhysPages(npages);
+
+ PortProxy &p = system->physProxy;
+ p.memsetBlob(paddr, 0, npages << LogVMPageSize);
+}
+
+
+template <class ISAOps>
+bool
+MultiLevelPageTable<ISAOps>::walk(Addr vaddr, bool allocate, Addr &PTE_addr)
+{
+ std::vector<uint64_t> offsets = pTableISAOps.getOffsets(vaddr);
+
+ Addr level_base = basePtr;
+ for (int i = numLevels - 1; i > 0; i--) {
+
+ Addr entry_addr = (level_base<<LogVMPageSize) +
+ offsets[i] * sizeof(PageTableEntry);
+
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