changeset 8c0870dbae5c in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=8c0870dbae5c
description:
ruby: slicc: change the way configurable members are specified
There are two changes this patch makes to the way configurable members
of a
state machine are specified in SLICC. The first change is that the data
member declarations will need to be separated by a semi-colon instead
of a
comma. Secondly, the default value to be assigned would now use SLICC's
assignment operator i.e. ':='.
diffstat:
src/mem/protocol/MESI_Three_Level-L0cache.sm | 12 ++++----
src/mem/protocol/MESI_Three_Level-L1cache.sm | 11 +++----
src/mem/protocol/MESI_Two_Level-L1cache.sm | 20 +++++++-------
src/mem/protocol/MESI_Two_Level-L2cache.sm | 8 ++--
src/mem/protocol/MESI_Two_Level-dir.sm | 8 ++--
src/mem/protocol/MESI_Two_Level-dma.sm | 4 +-
src/mem/protocol/MI_example-cache.sm | 10 +++---
src/mem/protocol/MI_example-dir.sm | 6 ++--
src/mem/protocol/MI_example-dma.sm | 4 +-
src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 14 +++++-----
src/mem/protocol/MOESI_CMP_directory-L2cache.sm | 6 ++--
src/mem/protocol/MOESI_CMP_directory-dir.sm | 6 ++--
src/mem/protocol/MOESI_CMP_directory-dma.sm | 6 ++--
src/mem/protocol/MOESI_CMP_token-L1cache.sm | 29 ++++++++++----------
src/mem/protocol/MOESI_CMP_token-L2cache.sm | 10 +++---
src/mem/protocol/MOESI_CMP_token-dir.sm | 14 +++++-----
src/mem/protocol/MOESI_CMP_token-dma.sm | 4 +-
src/mem/protocol/MOESI_hammer-cache.sm | 18 ++++++------
src/mem/protocol/MOESI_hammer-dir.sm | 12 ++++----
src/mem/protocol/MOESI_hammer-dma.sm | 4 +-
src/mem/protocol/Network_test-cache.sm | 4 +-
src/mem/slicc/ast/FormalParamAST.py | 1 +
src/mem/slicc/ast/ObjDeclAST.py | 3 +-
src/mem/slicc/ast/StallAndWaitStatementAST.py | 2 +-
src/mem/slicc/parser.py | 30 ++++++++++++++-------
src/mem/slicc/symbols/StateMachine.py | 35 +++++++++++++++----------
26 files changed, 149 insertions(+), 132 deletions(-)
diffs (truncated from 639 to 300 lines):
diff -r 6df951dcd7d9 -r 8c0870dbae5c
src/mem/protocol/MESI_Three_Level-L0cache.sm
--- a/src/mem/protocol/MESI_Three_Level-L0cache.sm Mon Sep 01 16:55:44
2014 -0500
+++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm Mon Sep 01 16:55:45
2014 -0500
@@ -27,12 +27,12 @@
*/
machine(L0Cache, "MESI Directory L0 Cache")
- : Sequencer * sequencer,
- CacheMemory * Icache,
- CacheMemory * Dcache,
- Cycles request_latency = 2,
- Cycles response_latency = 2,
- bool send_evictions,
+ : Sequencer * sequencer;
+ CacheMemory * Icache;
+ CacheMemory * Dcache;
+ Cycles request_latency := 2;
+ Cycles response_latency := 2;
+ bool send_evictions;
{
// NODE L0 CACHE
// From this node's L0 cache to the network
diff -r 6df951dcd7d9 -r 8c0870dbae5c
src/mem/protocol/MESI_Three_Level-L1cache.sm
--- a/src/mem/protocol/MESI_Three_Level-L1cache.sm Mon Sep 01 16:55:44
2014 -0500
+++ b/src/mem/protocol/MESI_Three_Level-L1cache.sm Mon Sep 01 16:55:45
2014 -0500
@@ -27,11 +27,11 @@
*/
machine(L1Cache, "MESI Directory L1 Cache CMP")
- : CacheMemory * cache,
- int l2_select_num_bits,
- Cycles l1_request_latency = 2,
- Cycles l1_response_latency = 2,
- Cycles to_l2_latency = 1,
+ : CacheMemory * cache;
+ int l2_select_num_bits;
+ Cycles l1_request_latency := 2;
+ Cycles l1_response_latency := 2;
+ Cycles to_l2_latency := 1;
{
// From this node's L1 cache TO the network
// a local L1 -> this L2 bank, currently ordered with directory forwarded
requests
@@ -40,7 +40,6 @@
MessageBuffer responseToL2, network="To", virtual_network="1",
ordered="false", vnet_type="response";
MessageBuffer unblockToL2, network="To", virtual_network="2",
ordered="false", vnet_type="unblock";
-
// To this node's L1 cache FROM the network
// a L2 bank -> this L1
MessageBuffer requestFromL2, network="From", virtual_network="0",
ordered="false", vnet_type="request";
diff -r 6df951dcd7d9 -r 8c0870dbae5c src/mem/protocol/MESI_Two_Level-L1cache.sm
--- a/src/mem/protocol/MESI_Two_Level-L1cache.sm Mon Sep 01 16:55:44
2014 -0500
+++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm Mon Sep 01 16:55:45
2014 -0500
@@ -27,16 +27,16 @@
*/
machine(L1Cache, "MESI Directory L1 Cache CMP")
- : Sequencer * sequencer,
- CacheMemory * L1Icache,
- CacheMemory * L1Dcache,
- Prefetcher * prefetcher = 'NULL',
- int l2_select_num_bits,
- Cycles l1_request_latency = 2,
- Cycles l1_response_latency = 2,
- Cycles to_l2_latency = 1,
- bool send_evictions,
- bool enable_prefetch = "False"
+ : Sequencer * sequencer;
+ CacheMemory * L1Icache;
+ CacheMemory * L1Dcache;
+ Prefetcher * prefetcher;
+ int l2_select_num_bits;
+ Cycles l1_request_latency := 2;
+ Cycles l1_response_latency := 2;
+ Cycles to_l2_latency := 1;
+ bool send_evictions;
+ bool enable_prefetch := "False";
{
// NODE L1 CACHE
// From this node's L1 cache TO the network
diff -r 6df951dcd7d9 -r 8c0870dbae5c src/mem/protocol/MESI_Two_Level-L2cache.sm
--- a/src/mem/protocol/MESI_Two_Level-L2cache.sm Mon Sep 01 16:55:44
2014 -0500
+++ b/src/mem/protocol/MESI_Two_Level-L2cache.sm Mon Sep 01 16:55:45
2014 -0500
@@ -32,10 +32,10 @@
*/
machine(L2Cache, "MESI Directory L2 Cache CMP")
- : CacheMemory * L2cache,
- Cycles l2_request_latency = 2,
- Cycles l2_response_latency = 2,
- Cycles to_l1_latency = 1
+ : CacheMemory * L2cache;
+ Cycles l2_request_latency := 2;
+ Cycles l2_response_latency := 2;
+ Cycles to_l1_latency := 1;
{
// L2 BANK QUEUES
// From local bank of L2 cache TO the network
diff -r 6df951dcd7d9 -r 8c0870dbae5c src/mem/protocol/MESI_Two_Level-dir.sm
--- a/src/mem/protocol/MESI_Two_Level-dir.sm Mon Sep 01 16:55:44 2014 -0500
+++ b/src/mem/protocol/MESI_Two_Level-dir.sm Mon Sep 01 16:55:45 2014 -0500
@@ -35,10 +35,10 @@
machine(Directory, "MESI Two Level directory protocol")
- : DirectoryMemory * directory,
- MemoryControl * memBuffer,
- Cycles to_mem_ctrl_latency = 1,
- Cycles directory_latency = 6,
+ : DirectoryMemory * directory;
+ MemoryControl * memBuffer;
+ Cycles to_mem_ctrl_latency := 1;
+ Cycles directory_latency := 6;
{
MessageBuffer requestToDir, network="From", virtual_network="0",
ordered="false", vnet_type="request";
diff -r 6df951dcd7d9 -r 8c0870dbae5c src/mem/protocol/MESI_Two_Level-dma.sm
--- a/src/mem/protocol/MESI_Two_Level-dma.sm Mon Sep 01 16:55:44 2014 -0500
+++ b/src/mem/protocol/MESI_Two_Level-dma.sm Mon Sep 01 16:55:45 2014 -0500
@@ -28,8 +28,8 @@
*/
machine(DMA, "DMA Controller")
-: DMASequencer * dma_sequencer,
- Cycles request_latency = 6
+: DMASequencer * dma_sequencer;
+ Cycles request_latency := 6;
{
MessageBuffer responseFromDir, network="From", virtual_network="1",
ordered="true", vnet_type="response";
diff -r 6df951dcd7d9 -r 8c0870dbae5c src/mem/protocol/MI_example-cache.sm
--- a/src/mem/protocol/MI_example-cache.sm Mon Sep 01 16:55:44 2014 -0500
+++ b/src/mem/protocol/MI_example-cache.sm Mon Sep 01 16:55:45 2014 -0500
@@ -28,11 +28,11 @@
*/
machine(L1Cache, "MI Example L1 Cache")
-: Sequencer * sequencer,
- CacheMemory * cacheMemory,
- Cycles cache_response_latency = 12,
- Cycles issue_latency = 2,
- bool send_evictions
+: Sequencer * sequencer;
+ CacheMemory * cacheMemory;
+ Cycles cache_response_latency := 12;
+ Cycles issue_latency := 2;
+ bool send_evictions;
{
// NETWORK BUFFERS
diff -r 6df951dcd7d9 -r 8c0870dbae5c src/mem/protocol/MI_example-dir.sm
--- a/src/mem/protocol/MI_example-dir.sm Mon Sep 01 16:55:44 2014 -0500
+++ b/src/mem/protocol/MI_example-dir.sm Mon Sep 01 16:55:45 2014 -0500
@@ -28,9 +28,9 @@
*/
machine(Directory, "Directory protocol")
-: DirectoryMemory * directory,
- MemoryControl * memBuffer,
- Cycles directory_latency = 12
+: DirectoryMemory * directory;
+ MemoryControl * memBuffer;
+ Cycles directory_latency := 12;
{
MessageBuffer forwardFromDir, network="To", virtual_network="3",
ordered="false", vnet_type="forward";
diff -r 6df951dcd7d9 -r 8c0870dbae5c src/mem/protocol/MI_example-dma.sm
--- a/src/mem/protocol/MI_example-dma.sm Mon Sep 01 16:55:44 2014 -0500
+++ b/src/mem/protocol/MI_example-dma.sm Mon Sep 01 16:55:45 2014 -0500
@@ -28,8 +28,8 @@
*/
machine(DMA, "DMA Controller")
-: DMASequencer * dma_sequencer,
- Cycles request_latency = 6
+: DMASequencer * dma_sequencer;
+ Cycles request_latency := 6;
{
MessageBuffer responseFromDir, network="From", virtual_network="1",
ordered="true", vnet_type="response";
diff -r 6df951dcd7d9 -r 8c0870dbae5c
src/mem/protocol/MOESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Mon Sep 01 16:55:44
2014 -0500
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Mon Sep 01 16:55:45
2014 -0500
@@ -27,13 +27,13 @@
*/
machine(L1Cache, "Directory protocol")
- : Sequencer * sequencer,
- CacheMemory * L1Icache,
- CacheMemory * L1Dcache,
- int l2_select_num_bits,
- Cycles request_latency = 2,
- Cycles use_timeout_latency = 50,
- bool send_evictions
+ : Sequencer * sequencer;
+ CacheMemory * L1Icache;
+ CacheMemory * L1Dcache;
+ int l2_select_num_bits;
+ Cycles request_latency := 2;
+ Cycles use_timeout_latency := 50;
+ bool send_evictions;
{
// NODE L1 CACHE
diff -r 6df951dcd7d9 -r 8c0870dbae5c
src/mem/protocol/MOESI_CMP_directory-L2cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm Mon Sep 01 16:55:44
2014 -0500
+++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm Mon Sep 01 16:55:45
2014 -0500
@@ -27,9 +27,9 @@
*/
machine(L2Cache, "Token protocol")
-: CacheMemory * L2cache,
- Cycles response_latency = 2,
- Cycles request_latency = 2
+: CacheMemory * L2cache;
+ Cycles response_latency := 2;
+ Cycles request_latency := 2;
{
// L2 BANK QUEUES
diff -r 6df951dcd7d9 -r 8c0870dbae5c src/mem/protocol/MOESI_CMP_directory-dir.sm
--- a/src/mem/protocol/MOESI_CMP_directory-dir.sm Mon Sep 01 16:55:44
2014 -0500
+++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm Mon Sep 01 16:55:45
2014 -0500
@@ -27,9 +27,9 @@
*/
machine(Directory, "Directory protocol")
-: DirectoryMemory * directory,
- MemoryControl * memBuffer,
- Cycles directory_latency = 6
+: DirectoryMemory * directory;
+ MemoryControl * memBuffer;
+ Cycles directory_latency := 6;
{
// ** IN QUEUES **
diff -r 6df951dcd7d9 -r 8c0870dbae5c src/mem/protocol/MOESI_CMP_directory-dma.sm
--- a/src/mem/protocol/MOESI_CMP_directory-dma.sm Mon Sep 01 16:55:44
2014 -0500
+++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm Mon Sep 01 16:55:45
2014 -0500
@@ -28,9 +28,9 @@
*/
machine(DMA, "DMA Controller")
-: DMASequencer * dma_sequencer,
- Cycles request_latency = 14,
- Cycles response_latency = 14
+: DMASequencer * dma_sequencer;
+ Cycles request_latency := 14;
+ Cycles response_latency := 14;
{
MessageBuffer responseFromDir, network="From", virtual_network="2",
ordered="false", vnet_type="response";
diff -r 6df951dcd7d9 -r 8c0870dbae5c src/mem/protocol/MOESI_CMP_token-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm Mon Sep 01 16:55:44
2014 -0500
+++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm Mon Sep 01 16:55:45
2014 -0500
@@ -32,22 +32,22 @@
*/
machine(L1Cache, "Token protocol")
- : Sequencer * sequencer,
- CacheMemory * L1Icache,
- CacheMemory * L1Dcache,
- int l2_select_num_bits,
- int N_tokens,
+ : Sequencer * sequencer;
+ CacheMemory * L1Icache;
+ CacheMemory * L1Dcache;
+ int l2_select_num_bits;
+ int N_tokens;
- Cycles l1_request_latency = 2,
- Cycles l1_response_latency = 2,
- int retry_threshold = 1,
- Cycles fixed_timeout_latency = 100,
- Cycles reissue_wakeup_latency = 10,
- Cycles use_timeout_latency = 50,
+ Cycles l1_request_latency := 2;
+ Cycles l1_response_latency := 2;
+ int retry_threshold := 1;
+ Cycles fixed_timeout_latency := 100;
+ Cycles reissue_wakeup_latency := 10;
+ Cycles use_timeout_latency := 50;
- bool dynamic_timeout_enabled = true,
- bool no_mig_atomic = true,
- bool send_evictions
+ bool dynamic_timeout_enabled := "True";
+ bool no_mig_atomic := "True";
+ bool send_evictions;
{
// From this node's L1 cache TO the network
@@ -206,7 +206,6 @@
Cycles averageLatencyEstimate() {
DPRINTF(RubySlicc, "%d\n",
(averageLatencyCounter >> averageLatencyHysteresis));
- //profile_average_latency_estimate( (averageLatencyCounter >>
averageLatencyHysteresis) );
return averageLatencyCounter >> averageLatencyHysteresis;
}
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
