changeset c00f6d7e2681 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c00f6d7e2681
description:
arch: Pass faults by const reference where possible
This patch changes how faults are passed between methods in an attempt
to copy as few reference-counting pointer instances as possible. This
should avoid unecessary copies being created, contributing to the
increment/decrement of the reference counters.
diffstat:
src/arch/arm/stage2_lookup.cc | 2 +-
src/arch/arm/stage2_lookup.hh | 2 +-
src/arch/arm/stage2_mmu.cc | 4 ++--
src/arch/arm/stage2_mmu.hh | 2 +-
src/cpu/checker/cpu.hh | 2 +-
src/cpu/checker/cpu_impl.hh | 2 +-
src/cpu/inorder/cpu.cc | 14 +++++++-------
src/cpu/inorder/cpu.hh | 15 ++++++++-------
src/cpu/inorder/inorder_dyn_inst.cc | 2 +-
src/cpu/inorder/inorder_dyn_inst.hh | 2 +-
src/cpu/inorder/resource.hh | 2 +-
src/cpu/inorder/resource_pool.cc | 2 +-
src/cpu/inorder/resource_pool.hh | 2 +-
src/cpu/inorder/resources/cache_unit.cc | 2 +-
src/cpu/inorder/resources/cache_unit.hh | 2 +-
src/cpu/inorder/resources/fetch_seq_unit.cc | 2 +-
src/cpu/inorder/resources/fetch_seq_unit.hh | 2 +-
src/cpu/inorder/resources/fetch_unit.cc | 2 +-
src/cpu/inorder/resources/fetch_unit.hh | 2 +-
src/cpu/minor/fetch1.cc | 4 ++--
src/cpu/minor/fetch1.hh | 4 ++--
src/cpu/minor/lsq.cc | 8 ++++----
src/cpu/minor/lsq.hh | 12 ++++++------
src/cpu/o3/cpu.cc | 4 ++--
src/cpu/o3/cpu.hh | 4 ++--
src/cpu/o3/dyn_inst.hh | 2 +-
src/cpu/o3/dyn_inst_impl.hh | 2 +-
src/cpu/o3/fetch.hh | 4 ++--
src/cpu/o3/fetch_impl.hh | 2 +-
src/cpu/ozone/dyn_inst_impl.hh | 2 +-
src/cpu/simple/base.cc | 2 +-
src/cpu/simple/base.hh | 2 +-
src/cpu/simple/timing.cc | 7 ++++---
src/cpu/simple/timing.hh | 8 ++++----
src/cpu/translation.hh | 4 ++--
src/sim/tlb.hh | 4 ++--
36 files changed, 71 insertions(+), 69 deletions(-)
diffs (truncated from 647 to 300 lines):
diff -r a3e23d599e11 -r c00f6d7e2681 src/arch/arm/stage2_lookup.cc
--- a/src/arch/arm/stage2_lookup.cc Fri Sep 19 10:35:14 2014 -0400
+++ b/src/arch/arm/stage2_lookup.cc Fri Sep 19 10:35:18 2014 -0400
@@ -171,7 +171,7 @@
}
void
-Stage2LookUp::finish(Fault _fault, RequestPtr req,
+Stage2LookUp::finish(const Fault &_fault, RequestPtr req,
ThreadContext *tc, BaseTLB::Mode mode)
{
fault = _fault;
diff -r a3e23d599e11 -r c00f6d7e2681 src/arch/arm/stage2_lookup.hh
--- a/src/arch/arm/stage2_lookup.hh Fri Sep 19 10:35:14 2014 -0400
+++ b/src/arch/arm/stage2_lookup.hh Fri Sep 19 10:35:18 2014 -0400
@@ -97,7 +97,7 @@
void markDelayed() {}
- void finish(Fault fault, RequestPtr req, ThreadContext *tc,
+ void finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
BaseTLB::Mode mode);
};
diff -r a3e23d599e11 -r c00f6d7e2681 src/arch/arm/stage2_mmu.cc
--- a/src/arch/arm/stage2_mmu.cc Fri Sep 19 10:35:14 2014 -0400
+++ b/src/arch/arm/stage2_mmu.cc Fri Sep 19 10:35:18 2014 -0400
@@ -114,8 +114,8 @@
}
void
-Stage2MMU::Stage2Translation::finish(Fault _fault, RequestPtr req,
ThreadContext *tc,
- BaseTLB::Mode mode)
+Stage2MMU::Stage2Translation::finish(const Fault &_fault, RequestPtr req,
+ ThreadContext *tc, BaseTLB::Mode mode)
{
fault = _fault;
diff -r a3e23d599e11 -r c00f6d7e2681 src/arch/arm/stage2_mmu.hh
--- a/src/arch/arm/stage2_mmu.hh Fri Sep 19 10:35:14 2014 -0400
+++ b/src/arch/arm/stage2_mmu.hh Fri Sep 19 10:35:18 2014 -0400
@@ -78,7 +78,7 @@
markDelayed() {}
void
- finish(Fault fault, RequestPtr req, ThreadContext *tc,
+ finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
BaseTLB::Mode mode);
void setVirt(Addr vaddr, int size, Request::Flags flags, int masterId)
diff -r a3e23d599e11 -r c00f6d7e2681 src/cpu/checker/cpu.hh
--- a/src/cpu/checker/cpu.hh Fri Sep 19 10:35:14 2014 -0400
+++ b/src/cpu/checker/cpu.hh Fri Sep 19 10:35:18 2014 -0400
@@ -426,7 +426,7 @@
void switchOut();
void takeOverFrom(BaseCPU *oldCPU);
- void advancePC(Fault fault);
+ void advancePC(const Fault &fault);
void verify(DynInstPtr &inst);
diff -r a3e23d599e11 -r c00f6d7e2681 src/cpu/checker/cpu_impl.hh
--- a/src/cpu/checker/cpu_impl.hh Fri Sep 19 10:35:14 2014 -0400
+++ b/src/cpu/checker/cpu_impl.hh Fri Sep 19 10:35:18 2014 -0400
@@ -69,7 +69,7 @@
template <class Impl>
void
-Checker<Impl>::advancePC(Fault fault)
+Checker<Impl>::advancePC(const Fault &fault)
{
if (fault != NoFault) {
curMacroStaticInst = StaticInst::nullStaticInstPtr;
diff -r a3e23d599e11 -r c00f6d7e2681 src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Fri Sep 19 10:35:14 2014 -0400
+++ b/src/cpu/inorder/cpu.cc Fri Sep 19 10:35:18 2014 -0400
@@ -128,8 +128,8 @@
}
InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
- Fault fault, ThreadID _tid, DynInstPtr inst,
- CPUEventPri event_pri)
+ const Fault &fault, ThreadID _tid,
+ DynInstPtr inst, CPUEventPri event_pri)
: Event(event_pri), cpu(_cpu)
{
setEvent(e_type, fault, _tid, inst);
@@ -910,7 +910,7 @@
}
void
-InOrderCPU::processInterrupts(Fault interrupt)
+InOrderCPU::processInterrupts(const Fault &interrupt)
{
// Check for interrupts here. For now can copy the code that
// exists within isa_fullsys_traits.hh. Also assume that thread 0
@@ -928,7 +928,7 @@
}
void
-InOrderCPU::trapContext(Fault fault, ThreadID tid, DynInstPtr inst,
+InOrderCPU::trapContext(const Fault &fault, ThreadID tid, DynInstPtr inst,
Cycles delay)
{
scheduleCpuEvent(Trap, fault, tid, inst, delay);
@@ -936,7 +936,7 @@
}
void
-InOrderCPU::trap(Fault fault, ThreadID tid, DynInstPtr inst)
+InOrderCPU::trap(const Fault &fault, ThreadID tid, DynInstPtr inst)
{
fault->invoke(tcBase(tid), inst->staticInst);
removePipelineStalls(tid);
@@ -970,7 +970,7 @@
}
void
-InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
+InOrderCPU::scheduleCpuEvent(CPUEventType c_event, const Fault &fault,
ThreadID tid, DynInstPtr inst,
Cycles delay, CPUEventPri event_pri)
{
@@ -1847,7 +1847,7 @@
}
void
-InOrderCPU::syscallContext(Fault fault, ThreadID tid, DynInstPtr inst,
+InOrderCPU::syscallContext(const Fault &fault, ThreadID tid, DynInstPtr inst,
Cycles delay)
{
// Syscall must be non-speculative, so squash from last stage
diff -r a3e23d599e11 -r c00f6d7e2681 src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh Fri Sep 19 10:35:14 2014 -0400
+++ b/src/cpu/inorder/cpu.hh Fri Sep 19 10:35:18 2014 -0400
@@ -263,11 +263,11 @@
public:
/** Constructs a CPU event. */
- CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
+ CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, const Fault &fault,
ThreadID _tid, DynInstPtr inst, CPUEventPri event_pri);
/** Set Type of Event To Be Scheduled */
- void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
+ void setEvent(CPUEventType e_type, const Fault &_fault, ThreadID _tid,
DynInstPtr _inst)
{
fault = _fault;
@@ -291,7 +291,8 @@
};
/** Schedule a CPU Event */
- void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
+ void scheduleCpuEvent(CPUEventType cpu_event, const Fault &fault,
+ ThreadID tid,
DynInstPtr inst, Cycles delay = Cycles(0),
CPUEventPri event_pri = InOrderCPU_Pri);
@@ -471,7 +472,7 @@
Fault getInterrupts();
/** Processes any an interrupt fault. */
- void processInterrupts(Fault interrupt);
+ void processInterrupts(const Fault &interrupt);
/** Halts the CPU. */
void halt() { panic("Halt not implemented!\n"); }
@@ -483,18 +484,18 @@
bool validDataAddr(Addr addr) { return true; }
/** Schedule a syscall on the CPU */
- void syscallContext(Fault fault, ThreadID tid, DynInstPtr inst,
+ void syscallContext(const Fault &fault, ThreadID tid, DynInstPtr inst,
Cycles delay = Cycles(0));
/** Executes a syscall.*/
void syscall(int64_t callnum, ThreadID tid);
/** Schedule a trap on the CPU */
- void trapContext(Fault fault, ThreadID tid, DynInstPtr inst,
+ void trapContext(const Fault &fault, ThreadID tid, DynInstPtr inst,
Cycles delay = Cycles(0));
/** Perform trap to Handle Given Fault */
- void trap(Fault fault, ThreadID tid, DynInstPtr inst);
+ void trap(const Fault &fault, ThreadID tid, DynInstPtr inst);
/** Schedule thread activation on the CPU */
void activateContext(ThreadID tid, Cycles delay = Cycles(0));
diff -r a3e23d599e11 -r c00f6d7e2681 src/cpu/inorder/inorder_dyn_inst.cc
--- a/src/cpu/inorder/inorder_dyn_inst.cc Fri Sep 19 10:35:14 2014 -0400
+++ b/src/cpu/inorder/inorder_dyn_inst.cc Fri Sep 19 10:35:18 2014 -0400
@@ -298,7 +298,7 @@
void
-InOrderDynInst::trap(Fault fault)
+InOrderDynInst::trap(const Fault &fault)
{
this->cpu->trap(fault, this->threadNumber, this);
}
diff -r a3e23d599e11 -r c00f6d7e2681 src/cpu/inorder/inorder_dyn_inst.hh
--- a/src/cpu/inorder/inorder_dyn_inst.hh Fri Sep 19 10:35:14 2014 -0400
+++ b/src/cpu/inorder/inorder_dyn_inst.hh Fri Sep 19 10:35:18 2014 -0400
@@ -524,7 +524,7 @@
/** Calls hardware return from error interrupt. */
Fault hwrei();
/** Traps to handle specified fault. */
- void trap(Fault fault);
+ void trap(const Fault &fault);
bool simPalCheck(int palFunc);
short syscallNum;
diff -r a3e23d599e11 -r c00f6d7e2681 src/cpu/inorder/resource.hh
--- a/src/cpu/inorder/resource.hh Fri Sep 19 10:35:14 2014 -0400
+++ b/src/cpu/inorder/resource.hh Fri Sep 19 10:35:18 2014 -0400
@@ -104,7 +104,7 @@
virtual void instGraduated(InstSeqNum seq_num, ThreadID tid) { }
/** Post-processsing for Trap Generated from this instruction */
- virtual void trap(Fault fault, ThreadID tid, DynInstPtr inst) { }
+ virtual void trap(const Fault &fault, ThreadID tid, DynInstPtr inst) { }
/** Request usage of this resource. Returns a ResourceRequest object
* with all the necessary resource information
diff -r a3e23d599e11 -r c00f6d7e2681 src/cpu/inorder/resource_pool.cc
--- a/src/cpu/inorder/resource_pool.cc Fri Sep 19 10:35:14 2014 -0400
+++ b/src/cpu/inorder/resource_pool.cc Fri Sep 19 10:35:18 2014 -0400
@@ -206,7 +206,7 @@
}
void
-ResourcePool::trap(Fault fault, ThreadID tid, DynInstPtr inst)
+ResourcePool::trap(const Fault &fault, ThreadID tid, DynInstPtr inst)
{
DPRINTF(Resource, "[tid:%i] Broadcasting Trap to all "
"resources.\n", tid);
diff -r a3e23d599e11 -r c00f6d7e2681 src/cpu/inorder/resource_pool.hh
--- a/src/cpu/inorder/resource_pool.hh Fri Sep 19 10:35:14 2014 -0400
+++ b/src/cpu/inorder/resource_pool.hh Fri Sep 19 10:35:18 2014 -0400
@@ -193,7 +193,7 @@
void instGraduated(InstSeqNum seq_num, ThreadID tid);
/** Broadcast trap to all resources */
- void trap(Fault fault, ThreadID tid, DynInstPtr inst);
+ void trap(const Fault &fault, ThreadID tid, DynInstPtr inst);
/** The number of instructions available that a resource can
* can still process.
diff -r a3e23d599e11 -r c00f6d7e2681 src/cpu/inorder/resources/cache_unit.cc
--- a/src/cpu/inorder/resources/cache_unit.cc Fri Sep 19 10:35:14 2014 -0400
+++ b/src/cpu/inorder/resources/cache_unit.cc Fri Sep 19 10:35:18 2014 -0400
@@ -405,7 +405,7 @@
}
void
-CacheUnit::trap(Fault fault, ThreadID tid, DynInstPtr inst)
+CacheUnit::trap(const Fault &fault, ThreadID tid, DynInstPtr inst)
{
tlbBlocked[tid] = false;
}
diff -r a3e23d599e11 -r c00f6d7e2681 src/cpu/inorder/resources/cache_unit.hh
--- a/src/cpu/inorder/resources/cache_unit.hh Fri Sep 19 10:35:14 2014 -0400
+++ b/src/cpu/inorder/resources/cache_unit.hh Fri Sep 19 10:35:18 2014 -0400
@@ -113,7 +113,7 @@
bool processSquash(CacheReqPacket *cache_pkt);
- void trap(Fault fault, ThreadID tid, DynInstPtr inst);
+ void trap(const Fault &fault, ThreadID tid, DynInstPtr inst);
void recvRetry();
diff -r a3e23d599e11 -r c00f6d7e2681 src/cpu/inorder/resources/fetch_seq_unit.cc
--- a/src/cpu/inorder/resources/fetch_seq_unit.cc Fri Sep 19 10:35:14
2014 -0400
+++ b/src/cpu/inorder/resources/fetch_seq_unit.cc Fri Sep 19 10:35:18
2014 -0400
@@ -304,7 +304,7 @@
}
void
-FetchSeqUnit::trap(Fault fault, ThreadID tid, DynInstPtr inst)
+FetchSeqUnit::trap(const Fault &fault, ThreadID tid, DynInstPtr inst)
{
pcValid[tid] = true;
pc[tid] = cpu->pcState(tid);
diff -r a3e23d599e11 -r c00f6d7e2681 src/cpu/inorder/resources/fetch_seq_unit.hh
--- a/src/cpu/inorder/resources/fetch_seq_unit.hh Fri Sep 19 10:35:14
2014 -0400
+++ b/src/cpu/inorder/resources/fetch_seq_unit.hh Fri Sep 19 10:35:18
2014 -0400
@@ -71,7 +71,7 @@
InstSeqNum squash_seq_num, ThreadID tid);
/** Update to correct PC from a trap */
- void trap(Fault fault, ThreadID tid, DynInstPtr inst);
+ void trap(const Fault &fault, ThreadID tid, DynInstPtr inst);
protected:
unsigned instSize;
diff -r a3e23d599e11 -r c00f6d7e2681 src/cpu/inorder/resources/fetch_unit.cc
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