[gem5-dev] changeset in gem5: cpu: Use a deque in o3 rename instruction queue

[Andreas Hansson via gem5-dev]

changeset a3e23d599e11 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a3e23d599e11
description:
        cpu: Use a deque in o3 rename instruction queue

        Switch from a list to a data structure with better data layout.

diffstat:

 src/cpu/o3/rename.hh |  9 ++++-----
 1 files changed, 4 insertions(+), 5 deletions(-)

diffs (20 lines):

diff -r 434228c914e5 -r a3e23d599e11 src/cpu/o3/rename.hh
--- a/src/cpu/o3/rename.hh      Fri Sep 19 10:35:12 2014 -0400
+++ b/src/cpu/o3/rename.hh      Fri Sep 19 10:35:14 2014 -0400
@@ -86,12 +86,11 @@
     // Typedefs from the ISA.
     typedef TheISA::RegIndex RegIndex;
 
-    // A list is used to queue the instructions.  Barrier insts must
-    // be added to the front of the list, which is the only reason for
-    // using a list instead of a queue. (Most other stages use a
+    // A deque is used to queue the instructions. Barrier insts must
+    // be added to the front of the queue, which is the only reason for
+    // using a deque instead of a queue. (Most other stages use a
     // queue)
-    typedef std::list<DynInstPtr> InstQueue;
-    typedef typename std::list<DynInstPtr>::iterator ListIt;
+    typedef std::deque<DynInstPtr> InstQueue;
 
   public:
     /** Overall rename status. Used to determine if the CPU can
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