changeset 7a618c07e663 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=7a618c07e663
description:
mem: Rename Bus to XBar to better reflect its behaviour
This patch changes the name of the Bus classes to XBar to better
reflect the actual timing behaviour. The actual instances in the
config scripts are not renamed, and remain as e.g. iobus or membus.
As part of this renaming, the code has also been clean up slightly,
making use of range-based for loops and tidying up some comments. The
only changes outside the bus/crossbar code is due to the delay
variables in the packet.
diffstat:
configs/common/CacheConfig.py | 4 +-
configs/common/FSConfig.py | 14 +-
configs/dram/sweep.py | 4 +-
configs/example/memtest.py | 4 +-
configs/example/ruby_mem_test.py | 2 +-
configs/example/se.py | 2 +-
configs/splash2/cluster.py | 10 +-
configs/splash2/run.py | 4 +-
src/arch/x86/pagetable_walker.cc | 2 +-
src/cpu/BaseCPU.py | 8 +-
src/dev/io_device.cc | 6 +-
src/dev/pcidev.cc | 2 +-
src/dev/x86/intdev.hh | 2 +-
src/mem/Bus.py | 85 ---
src/mem/SConscript | 28 +-
src/mem/XBar.py | 85 +++
src/mem/bridge.cc | 12 +-
src/mem/bridge.hh | 12 +-
src/mem/bus.cc | 622 ------------------------
src/mem/bus.hh | 401 ---------------
src/mem/cache/cache_impl.hh | 30 +-
src/mem/coherent_bus.cc | 830 ---------------------------------
src/mem/coherent_bus.hh | 399 ---------------
src/mem/coherent_xbar.cc | 813 ++++++++++++++++++++++++++++++++
src/mem/coherent_xbar.hh | 397 +++++++++++++++
src/mem/dram_ctrl.cc | 2 +-
src/mem/dramsim2.cc | 2 +-
src/mem/noncoherent_bus.cc | 306 ------------
src/mem/noncoherent_bus.hh | 211 --------
src/mem/noncoherent_xbar.cc | 302 ++++++++++++
src/mem/noncoherent_xbar.hh | 211 ++++++++
src/mem/packet.hh | 57 +-
src/mem/physical.cc | 8 +-
src/mem/simple_mem.cc | 2 +-
src/mem/xbar.cc | 614 ++++++++++++++++++++++++
src/mem/xbar.hh | 388 +++++++++++++++
src/python/m5/params.py | 2 +-
src/python/m5/util/dot_writer.py | 8 +-
tests/configs/base_config.py | 4 +-
tests/configs/memtest-filter.py | 8 +-
tests/configs/memtest-ruby.py | 2 +-
tests/configs/memtest.py | 6 +-
tests/configs/o3-timing-mp-ruby.py | 2 +-
tests/configs/o3-timing-ruby.py | 2 +-
tests/configs/simple-atomic-mp-ruby.py | 2 +-
tests/configs/tgen-dram-ctrl.py | 2 +-
tests/configs/tgen-simple-mem.py | 2 +-
47 files changed, 2937 insertions(+), 2984 deletions(-)
diffs (truncated from 6699 to 300 lines):
diff -r 560aead2320f -r 7a618c07e663 configs/common/CacheConfig.py
--- a/configs/common/CacheConfig.py Sat Sep 20 17:18:30 2014 -0400
+++ b/configs/common/CacheConfig.py Sat Sep 20 17:18:32 2014 -0400
@@ -71,8 +71,8 @@
size=options.l2_size,
assoc=options.l2_assoc)
- system.tol2bus = CoherentBus(clk_domain = system.cpu_clk_domain,
- width = 32)
+ system.tol2bus = CoherentXBar(clk_domain = system.cpu_clk_domain,
+ width = 32)
system.l2.cpu_side = system.tol2bus.master
system.l2.mem_side = system.membus.slave
diff -r 560aead2320f -r 7a618c07e663 configs/common/FSConfig.py
--- a/configs/common/FSConfig.py Sat Sep 20 17:18:30 2014 -0400
+++ b/configs/common/FSConfig.py Sat Sep 20 17:18:32 2014 -0400
@@ -50,7 +50,7 @@
def childImage(self, ci):
self.image.child.image_file = ci
-class MemBus(CoherentBus):
+class MemBus(CoherentXBar):
badaddr_responder = BadAddr()
default = Self.badaddr_responder.pio
@@ -71,7 +71,7 @@
self.tsunami = BaseTsunami()
# Create the io bus to connect all device ports
- self.iobus = NoncoherentBus()
+ self.iobus = NoncoherentXBar()
self.tsunami.attachIO(self.iobus)
self.tsunami.ide.pio = self.iobus.master
@@ -134,7 +134,7 @@
# generic system
mdesc = SysConfig()
self.readfile = mdesc.script()
- self.iobus = NoncoherentBus()
+ self.iobus = NoncoherentXBar()
self.membus = MemBus()
self.bridge = Bridge(delay='50ns')
self.t1000 = T1000()
@@ -196,7 +196,7 @@
mdesc = SysConfig()
self.readfile = mdesc.script()
- self.iobus = NoncoherentBus()
+ self.iobus = NoncoherentXBar()
self.membus = MemBus()
self.membus.badaddr_responder.warn_access = "warn"
self.bridge = Bridge(delay='50ns')
@@ -299,7 +299,7 @@
# generic system
mdesc = SysConfig()
self.readfile = mdesc.script()
- self.iobus = NoncoherentBus()
+ self.iobus = NoncoherentXBar()
self.membus = MemBus()
self.bridge = Bridge(delay='50ns')
self.mem_ranges = [AddrRange('1GB')]
@@ -344,7 +344,7 @@
x86_sys.membus = MemBus()
# North Bridge
- x86_sys.iobus = NoncoherentBus()
+ x86_sys.iobus = NoncoherentXBar()
x86_sys.bridge = Bridge(delay='50ns')
x86_sys.bridge.master = x86_sys.iobus.slave
x86_sys.bridge.slave = x86_sys.membus.master
@@ -379,7 +379,7 @@
def connectX86RubySystem(x86_sys):
# North Bridge
- x86_sys.iobus = NoncoherentBus()
+ x86_sys.iobus = NoncoherentXBar()
# add the ide to the list of dma devices that later need to attach to
# dma controllers
diff -r 560aead2320f -r 7a618c07e663 configs/dram/sweep.py
--- a/configs/dram/sweep.py Sat Sep 20 17:18:30 2014 -0400
+++ b/configs/dram/sweep.py Sat Sep 20 17:18:32 2014 -0400
@@ -82,9 +82,9 @@
# and address mapping
# start with the system itself, using a multi-layer 1.5 GHz
-# bus/crossbar, delivering 64 bytes / 5 cycles (one header cycle)
+# crossbar, delivering 64 bytes / 5 cycles (one header cycle)
# which amounts to 19.2 GByte/s per layer and thus per port
-system = System(membus = NoncoherentBus(width = 16))
+system = System(membus = NoncoherentXBar(width = 16))
system.clk_domain = SrcClockDomain(clock = '1.5GHz',
voltage_domain =
VoltageDomain(voltage = '1V'))
diff -r 560aead2320f -r 7a618c07e663 configs/example/memtest.py
--- a/configs/example/memtest.py Sat Sep 20 17:18:30 2014 -0400
+++ b/configs/example/memtest.py Sat Sep 20 17:18:32 2014 -0400
@@ -147,7 +147,7 @@
# system simulated
system = System(funcmem = SimpleMemory(in_addr_map = False),
- funcbus = NoncoherentBus(),
+ funcbus = NoncoherentXBar(),
physmem = SimpleMemory(latency = "100ns"),
cache_line_size = block_size)
@@ -162,7 +162,7 @@
parent = attach_obj # use attach obj as config parent too
if len(spec) > 1 and (fanout > 1 or options.force_bus):
port = getattr(attach_obj, attach_port)
- new_bus = CoherentBus(width=16)
+ new_bus = CoherentXBar(width=16)
if (port.role == 'MASTER'):
new_bus.slave = port
attach_port = "master"
diff -r 560aead2320f -r 7a618c07e663 configs/example/ruby_mem_test.py
--- a/configs/example/ruby_mem_test.py Sat Sep 20 17:18:30 2014 -0400
+++ b/configs/example/ruby_mem_test.py Sat Sep 20 17:18:32 2014 -0400
@@ -106,7 +106,7 @@
system = System(cpu = cpus,
funcmem = SimpleMemory(in_addr_map = False),
- funcbus = NoncoherentBus(),
+ funcbus = NoncoherentXBar(),
physmem = SimpleMemory(),
clk_domain = SrcClockDomain(clock = options.sys_clock),
mem_ranges = [AddrRange(options.mem_size)])
diff -r 560aead2320f -r 7a618c07e663 configs/example/se.py
--- a/configs/example/se.py Sat Sep 20 17:18:30 2014 -0400
+++ b/configs/example/se.py Sat Sep 20 17:18:32 2014 -0400
@@ -255,7 +255,7 @@
system.cpu[i].dtb.walker.port = ruby_port.slave
else:
MemClass = Simulation.setMemClass(options)
- system.membus = CoherentBus()
+ system.membus = CoherentXBar()
system.system_port = system.membus.slave
CacheConfig.config_cache(options, system)
MemConfig.config_mem(options, system)
diff -r 560aead2320f -r 7a618c07e663 configs/splash2/cluster.py
--- a/configs/splash2/cluster.py Sat Sep 20 17:18:30 2014 -0400
+++ b/configs/splash2/cluster.py Sat Sep 20 17:18:32 2014 -0400
@@ -171,7 +171,7 @@
for j in xrange(options.numclusters):
clusters[j].id = j
for cluster in clusters:
- cluster.clusterbus = CoherentBus(clock=busFrequency)
+ cluster.clusterbus = CoherentXBar(clock=busFrequency)
all_l1buses += [cluster.clusterbus]
cluster.cpus = [TimingSimpleCPU(cpu_id = i + cluster.id,
clock=options.frequency)
@@ -184,7 +184,7 @@
for j in xrange(options.numclusters):
clusters[j].id = j
for cluster in clusters:
- cluster.clusterbus = CoherentBus(clock=busFrequency)
+ cluster.clusterbus = CoherentXBar(clock=busFrequency)
all_l1buses += [cluster.clusterbus]
cluster.cpus = [DerivO3CPU(cpu_id = i + cluster.id,
clock=options.frequency)
@@ -197,7 +197,7 @@
for j in xrange(options.numclusters):
clusters[j].id = j
for cluster in clusters:
- cluster.clusterbus = CoherentBus(clock=busFrequency)
+ cluster.clusterbus = CoherentXBar(clock=busFrequency)
all_l1buses += [cluster.clusterbus]
cluster.cpus = [AtomicSimpleCPU(cpu_id = i + cluster.id,
clock=options.frequency)
@@ -211,10 +211,10 @@
# ----------------------
system = System(cpu = all_cpus, l1_ = all_l1s, l1bus_ = all_l1buses,
physmem = SimpleMemory(),
- membus = CoherentBus(clock = busFrequency))
+ membus = CoherentXBar(clock = busFrequency))
system.clock = '1GHz'
-system.toL2bus = CoherentBus(clock = busFrequency)
+system.toL2bus = CoherentXBar(clock = busFrequency)
system.l2 = L2(size = options.l2size, assoc = 8)
# ----------------------
diff -r 560aead2320f -r 7a618c07e663 configs/splash2/run.py
--- a/configs/splash2/run.py Sat Sep 20 17:18:30 2014 -0400
+++ b/configs/splash2/run.py Sat Sep 20 17:18:32 2014 -0400
@@ -196,10 +196,10 @@
# Create a system, and add system wide objects
# ----------------------
system = System(cpu = cpus, physmem = SimpleMemory(),
- membus = CoherentBus(clock = busFrequency))
+ membus = CoherentXBar(clock = busFrequency))
system.clock = '1GHz'
-system.toL2bus = CoherentBus(clock = busFrequency)
+system.toL2bus = CoherentXBar(clock = busFrequency)
system.l2 = L2(size = options.l2size, assoc = 8)
# ----------------------
diff -r 560aead2320f -r 7a618c07e663 src/arch/x86/pagetable_walker.cc
--- a/src/arch/x86/pagetable_walker.cc Sat Sep 20 17:18:30 2014 -0400
+++ b/src/arch/x86/pagetable_walker.cc Sat Sep 20 17:18:32 2014 -0400
@@ -597,7 +597,7 @@
assert(!read);
// @todo someone should pay for this
- pkt->busFirstWordDelay = pkt->busLastWordDelay = 0;
+ pkt->firstWordDelay = pkt->lastWordDelay = 0;
state = nextState;
nextState = Ready;
diff -r 560aead2320f -r 7a618c07e663 src/cpu/BaseCPU.py
--- a/src/cpu/BaseCPU.py Sat Sep 20 17:18:30 2014 -0400
+++ b/src/cpu/BaseCPU.py Sat Sep 20 17:18:32 2014 -0400
@@ -47,7 +47,7 @@
from m5.params import *
from m5.proxy import *
-from Bus import CoherentBus
+from XBar import CoherentXBar
from InstTracer import InstTracer
from ExeTracer import ExeTracer
from MemObject import MemObject
@@ -274,8 +274,8 @@
self.itb_walker_cache = iwc
self.dtb_walker_cache = dwc
if buildEnv['TARGET_ISA'] in ['arm']:
- self.itb_walker_cache_bus = CoherentBus()
- self.dtb_walker_cache_bus = CoherentBus()
+ self.itb_walker_cache_bus = CoherentXBar()
+ self.dtb_walker_cache_bus = CoherentXBar()
self.itb_walker_cache_bus.master = iwc.cpu_side
self.dtb_walker_cache_bus.master = dwc.cpu_side
self.itb.walker.port = self.itb_walker_cache_bus.slave
@@ -308,7 +308,7 @@
# Set a width of 32 bytes (256-bits), which is four times that
# of the default bus. The clock of the CPU is inherited by
# default.
- self.toL2Bus = CoherentBus(width = 32)
+ self.toL2Bus = CoherentXBar(width = 32)
self.connectCachedPorts(self.toL2Bus)
self.l2cache = l2c
self.toL2Bus.master = self.l2cache.cpu_side
diff -r 560aead2320f -r 7a618c07e663 src/dev/io_device.cc
--- a/src/dev/io_device.cc Sat Sep 20 17:18:30 2014 -0400
+++ b/src/dev/io_device.cc Sat Sep 20 17:18:32 2014 -0400
@@ -42,7 +42,7 @@
*/
#include "base/trace.hh"
-#include "debug/BusAddrRanges.hh"
+#include "debug/AddrRanges.hh"
#include "dev/io_device.hh"
#include "sim/system.hh"
@@ -55,7 +55,7 @@
PioPort::recvAtomic(PacketPtr pkt)
{
// @todo: We need to pay for this and not just zero it out
- pkt->busFirstWordDelay = pkt->busLastWordDelay = 0;
+ pkt->firstWordDelay = pkt->lastWordDelay = 0;
return pkt->isRead() ? device->read(pkt) : device->write(pkt);
}
@@ -113,7 +113,7 @@
{
assert(pioSize != 0);
AddrRangeList ranges;
- DPRINTF(BusAddrRanges, "registering range: %#x-%#x\n", pioAddr, pioSize);
+ DPRINTF(AddrRanges, "registering range: %#x-%#x\n", pioAddr, pioSize);
ranges.push_back(RangeSize(pioAddr, pioSize));
return ranges;
}
diff -r 560aead2320f -r 7a618c07e663 src/dev/pcidev.cc
--- a/src/dev/pcidev.cc Sat Sep 20 17:18:30 2014 -0400
+++ b/src/dev/pcidev.cc Sat Sep 20 17:18:32 2014 -0400
@@ -80,7 +80,7 @@
assert(pkt->getAddr() >= configAddr &&
pkt->getAddr() < configAddr + PCI_CONFIG_SIZE);
// @todo someone should pay for this
- pkt->busFirstWordDelay = pkt->busLastWordDelay = 0;
+ pkt->firstWordDelay = pkt->lastWordDelay = 0;
return pkt->isRead() ? device->readConfig(pkt) : device->writeConfig(pkt);
}
diff -r 560aead2320f -r 7a618c07e663 src/dev/x86/intdev.hh
--- a/src/dev/x86/intdev.hh Sat Sep 20 17:18:30 2014 -0400
+++ b/src/dev/x86/intdev.hh Sat Sep 20 17:18:32 2014 -0400
@@ -82,7 +82,7 @@
Tick recvMessage(PacketPtr pkt)
{
// @todo someone should pay for this
- pkt->busFirstWordDelay = pkt->busLastWordDelay = 0;
+ pkt->firstWordDelay = pkt->lastWordDelay = 0;
return device->recvMessage(pkt);
}
};
diff -r 560aead2320f -r 7a618c07e663 src/mem/Bus.py
--- a/src/mem/Bus.py Sat Sep 20 17:18:30 2014 -0400
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
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