changeset d96740732a61 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d96740732a61
description:
stats: update t1000 stats for recent changes
diffstat:
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
| 26 +-
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json
| 478 ++++++---
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr
| 12 +
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
| 4 +-
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
| 202 ++-
5 files changed, 468 insertions(+), 254 deletions(-)
diffs (truncated from 1231 to 300 lines):
diff -r 2b1bb16fd3d0 -r d96740732a61
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
---
a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
Sun Sep 21 16:15:14 2014 -0400
+++
b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
Sun Sep 21 23:04:39 2014 -0400
@@ -16,10 +16,10 @@
clk_domain=system.clk_domain
eventq_index=0
hypervisor_addr=1099243257856
-hypervisor_bin=/scratch/nilay/GEM5/system/binaries/q_new.bin
+hypervisor_bin=/dist/m5/system/binaries/q_new.bin
hypervisor_desc=system.hypervisor_desc
hypervisor_desc_addr=133446500352
-hypervisor_desc_bin=/scratch/nilay/GEM5/system/binaries/1up-hv.bin
+hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin
init_param=0
kernel=
kernel_addr_check=true
@@ -27,19 +27,19 @@
load_offset=0
mem_mode=atomic
mem_ranges=1048576:68157439 2147483648:2415919103
-memories=system.partition_desc system.rom system.nvram system.physmem1
system.hypervisor_desc system.physmem0
+memories=system.hypervisor_desc system.physmem1 system.partition_desc
system.physmem0 system.rom system.nvram
num_work_ids=16
nvram=system.nvram
nvram_addr=133429198848
-nvram_bin=/scratch/nilay/GEM5/system/binaries/nvram1
+nvram_bin=/dist/m5/system/binaries/nvram1
openboot_addr=1099243716608
-openboot_bin=/scratch/nilay/GEM5/system/binaries/openboot_new.bin
+openboot_bin=/dist/m5/system/binaries/openboot_new.bin
partition_desc=system.partition_desc
partition_desc_addr=133445976064
-partition_desc_bin=/scratch/nilay/GEM5/system/binaries/1up-md.bin
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+partition_desc_bin=/dist/m5/system/binaries/1up-md.bin
+readfile=/z/stever/hg/gem5/tests/halt.sh
reset_addr=1099243192320
-reset_bin=/scratch/nilay/GEM5/system/binaries/reset_new.bin
+reset_bin=/dist/m5/system/binaries/reset_new.bin
rom=system.rom
symbolfile=
work_begin_ckpt_count=0
@@ -95,9 +95,6 @@
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -163,7 +160,7 @@
[system.disk0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/disk.s10hw2
+image_file=/dist/m5/system/disks/disk.s10hw2
read_only=true
[system.dvfs_handler]
@@ -193,7 +190,7 @@
sys=system
[system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
@@ -203,11 +200,12 @@
slave=system.bridge.master
[system.membus]
-type=CoherentBus
+type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff -r 2b1bb16fd3d0 -r d96740732a61
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json
---
a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json
Sun Sep 21 16:15:14 2014 -0400
+++
b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json
Sun Sep 21 23:04:39 2014 -0400
@@ -2,30 +2,16 @@
"name": null,
"sim_quantum": 0,
"system": {
- "bridge": {
- "slave": {
- "peer": "system.membus.master[2]",
- "role": "SLAVE"
- },
- "name": "bridge",
- "req_size": 16,
- "delay": 5.0000000000000004e-08,
- "eventq_index": 0,
- "master": {
- "peer": "system.iobus.slave[0]",
- "role": "MASTER"
- },
- "cxx_class": "Bridge",
- "path": "system.bridge",
- "resp_size": 16,
- "type": "Bridge"
- },
+ "kernel": "",
"kernel_addr_check": true,
"rom": {
- "latency": 3.0000000000000004e-08,
+ "range": "1099243192320:1099251580927",
+ "latency": 60,
"name": "rom",
"eventq_index": 0,
- "latency_var": 0.0,
+ "clk_domain": "system.clk_domain",
+ "latency_var": 0,
+ "bandwidth": "0.000000",
"conf_table_reported": true,
"cxx_class": "SimpleMemory",
"path": "system.rom",
@@ -37,62 +23,31 @@
},
"in_addr_map": true
},
- "membus": {
+ "bridge": {
+ "ranges": [
+ "133412421632:133412421639",
+ "134217728000:554050781183",
+ "644245094400:652835028991",
+ "725849473024:1095485095935",
+ "1099255955456:1099255955463"
+ ],
"slave": {
- "peer": [
- "system.system_port",
- "system.cpu.icache_port",
- "system.cpu.dcache_port"
- ],
+ "peer": "system.membus.master[2]",
"role": "SLAVE"
},
- "name": "membus",
- "badaddr_responder": {
- "ret_data8": 255,
- "name": "badaddr_responder",
- "pio": {
- "peer": "system.membus.default",
- "role": "SLAVE"
- },
- "ret_bad_addr": true,
- "pio_latency": 1.0000000000000001e-07,
- "fake_mem": false,
- "pio_size": 8,
- "ret_data32": 4294967295,
- "eventq_index": 0,
- "update_data": false,
- "ret_data64": 18446744073709551615,
- "cxx_class": "IsaFake",
- "path": "system.membus.badaddr_responder",
- "pio_addr": 0,
- "type": "IsaFake",
- "ret_data16": 65535
- },
- "default": {
- "peer": "system.membus.badaddr_responder.pio",
+ "name": "bridge",
+ "req_size": 16,
+ "clk_domain": "system.clk_domain",
+ "delay": 100,
+ "eventq_index": 0,
+ "master": {
+ "peer": "system.iobus.slave[0]",
"role": "MASTER"
},
- "header_cycles": 1,
- "width": 8,
- "eventq_index": 0,
- "master": {
- "peer": [
- "system.t1000.iob.pio",
- "system.t1000.htod.pio",
- "system.bridge.slave",
- "system.rom.port",
- "system.nvram.port",
- "system.hypervisor_desc.port",
- "system.partition_desc.port",
- "system.physmem0.port",
- "system.physmem1.port"
- ],
- "role": "MASTER"
- },
- "cxx_class": "CoherentBus",
- "path": "system.membus",
- "type": "CoherentBus",
- "use_default_range": false
+ "cxx_class": "Bridge",
+ "path": "system.bridge",
+ "resp_size": 16,
+ "type": "Bridge"
},
"iobus": {
"slave": {
@@ -102,6 +57,7 @@
"role": "SLAVE"
},
"name": "iobus",
+ "clk_domain": "system.clk_domain",
"header_cycles": 1,
"width": 8,
"eventq_index": 0,
@@ -125,9 +81,9 @@
],
"role": "MASTER"
},
- "cxx_class": "NoncoherentBus",
+ "cxx_class": "NoncoherentXBar",
"path": "system.iobus",
- "type": "NoncoherentBus",
+ "type": "NoncoherentXBar",
"use_default_range": false
},
"t1000": {
@@ -138,7 +94,9 @@
"role": "SLAVE"
},
"time": "Thu Jan 1 00:00:00 2009",
- "pio_latency": 1.0000000000000001e-07,
+ "pio_latency": 200,
+ "clk_domain": "system.clk_domain",
+ "system": "system",
"eventq_index": 0,
"cxx_class": "DumbTOD",
"path": "system.t1000.htod",
@@ -151,7 +109,11 @@
"peer": "system.iobus.master[12]",
"role": "SLAVE"
},
- "pio_latency": 1.0000000000000001e-07,
+ "pio_latency": 200,
+ "clk_domain": "system.clk_domain",
+ "system": "system",
+ "terminal": "system.t1000.pterm",
+ "platform": "system.t1000",
"eventq_index": 0,
"cxx_class": "Uart8250",
"path": "system.t1000.puart0",
@@ -159,14 +121,17 @@
"type": "Uart8250"
},
"fake_membnks": {
+ "system": "system",
"ret_data8": 255,
"name": "fake_membnks",
+ "warn_access": "",
"pio": {
"peer": "system.iobus.master[1]",
"role": "SLAVE"
},
"ret_bad_addr": false,
- "pio_latency": 1.0000000000000001e-07,
+ "pio_latency": 200,
+ "clk_domain": "system.clk_domain",
"fake_mem": false,
"pio_size": 16384,
"ret_data32": 4294967295,
@@ -181,14 +146,17 @@
},
"cxx_class": "T1000",
"fake_jbi": {
+ "system": "system",
"ret_data8": 255,
"name": "fake_jbi",
+ "warn_access": "",
"pio": {
"peer": "system.iobus.master[11]",
"role": "SLAVE"
},
"ret_bad_addr": false,
- "pio_latency": 1.0000000000000001e-07,
+ "pio_latency": 200,
+ "clk_domain": "system.clk_domain",
"fake_mem": false,
"pio_size": 4294967296,
"ret_data32": 4294967295,
@@ -201,15 +169,19 @@
"type": "IsaFake",
"ret_data16": 65535
},
+ "intrctrl": "system.intrctrl",
"fake_l2esr_2": {
+ "system": "system",
"ret_data8": 255,
"name": "fake_l2esr_2",
+ "warn_access": "",
"pio": {
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