changeset a910aeb89098 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a910aeb89098
description:
mem: Add packet sanity checks to cache and MSHRs
This patch adds a number of asserts to the cache, checking basic
assumptions about packets being requests or responses.
diffstat:
src/mem/cache/cache.hh | 2 +-
src/mem/cache/cache_impl.hh | 13 +++++++++++++
src/mem/cache/mshr.cc | 2 ++
3 files changed, 16 insertions(+), 1 deletions(-)
diffs (82 lines):
diff -r cc7f3988c5a9 -r a910aeb89098 src/mem/cache/cache.hh
--- a/src/mem/cache/cache.hh Thu Oct 09 17:51:52 2014 -0400
+++ b/src/mem/cache/cache.hh Thu Oct 09 17:51:56 2014 -0400
@@ -380,7 +380,7 @@
* are successfully sent.
* @param pkt The request that was sent on the bus.
*/
- void markInService(MSHR *mshr, PacketPtr pkt = 0);
+ void markInService(MSHR *mshr, PacketPtr pkt = NULL);
/**
* Return whether there are any outstanding misses.
diff -r cc7f3988c5a9 -r a910aeb89098 src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh Thu Oct 09 17:51:52 2014 -0400
+++ b/src/mem/cache/cache_impl.hh Thu Oct 09 17:51:56 2014 -0400
@@ -107,6 +107,8 @@
void
Cache<TagStore>::cmpAndSwap(BlkType *blk, PacketPtr pkt)
{
+ assert(pkt->isRequest());
+
uint64_t overwrite_val;
bool overwrite_mem;
uint64_t condition_val64;
@@ -149,6 +151,8 @@
bool deferred_response,
bool pending_downgrade)
{
+ assert(pkt->isRequest());
+
assert(blk && blk->isValid());
// Occasionally this is not true... if we are a lower-level cache
// satisfying a string of Read and ReadEx requests from
@@ -247,6 +251,8 @@
void
Cache<TagStore>::markInService(MSHR *mshr, PacketPtr pkt)
{
+ // packet can be either a request or response
+
markInServiceInternal(mshr, pkt);
#if 0
if (mshr->originalCmd == MemCmd::HardPFReq) {
@@ -295,6 +301,9 @@
Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
Cycles &lat, PacketList &writebacks)
{
+ // sanity check
+ assert(pkt->isRequest());
+
DPRINTF(Cache, "%s for %s address %x size %d\n", __func__,
pkt->cmdString(), pkt->getAddr(), pkt->getSize());
if (pkt->req->isUncacheable()) {
@@ -1431,6 +1440,7 @@
Cache<TagStore>::handleFill(PacketPtr pkt, BlkType *blk,
PacketList &writebacks)
{
+ assert(pkt->isResponse());
Addr addr = pkt->getAddr();
bool is_secure = pkt->isSecure();
#if TRACING_ON
@@ -1516,6 +1526,9 @@
doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
bool already_copied, bool pending_inval)
{
+ // sanity check
+ assert(req_pkt->isRequest());
+
DPRINTF(Cache, "%s for %s address %x size %d\n", __func__,
req_pkt->cmdString(), req_pkt->getAddr(), req_pkt->getSize());
// timing-mode snoop responses require a new packet, unless we
diff -r cc7f3988c5a9 -r a910aeb89098 src/mem/cache/mshr.cc
--- a/src/mem/cache/mshr.cc Thu Oct 09 17:51:52 2014 -0400
+++ b/src/mem/cache/mshr.cc Thu Oct 09 17:51:56 2014 -0400
@@ -247,6 +247,8 @@
popTarget();
return true;
}
+
+ assert(pkt != NULL);
inService = true;
pendingDirty = (targets.needsExclusive ||
(!pkt->sharedAsserted() && pkt->memInhibitAsserted()));
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
