Hello, I am trying to understand how the CPU is accessing the cache in Gem5. From the documentation (http://www.gem5.org/docs/html/gem5MemorySystem.html), it says: " (CPU) Read access is initiated by sending message to the port towards DCache object." I tried to find the corresponding code but hasn't been able to pinpoint it. Can anybody help me explain a little bit about how the CPU read access is happening in the code? Which classe/method is the initiator of this CPU access?
Thanks, Jason Geng _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
