changeset 1e3b3c7a0cba in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=1e3b3c7a0cba
description:
mem: Page Table long lines
Trimmed down all the lines greater than 78 characters.
diffstat:
src/mem/multi_level_page_table.hh | 3 ++-
src/mem/multi_level_page_table_impl.hh | 21 ++++++++++++++-------
src/mem/page_table.cc | 9 ++++++---
src/mem/page_table.hh | 3 ++-
4 files changed, 24 insertions(+), 12 deletions(-)
diffs (132 lines):
diff -r 9f456b5cc474 -r 1e3b3c7a0cba src/mem/multi_level_page_table.hh
--- a/src/mem/multi_level_page_table.hh Sun Nov 23 18:01:08 2014 -0800
+++ b/src/mem/multi_level_page_table.hh Sun Nov 23 18:01:09 2014 -0800
@@ -141,7 +141,8 @@
bool walk(Addr vaddr, bool allocate, Addr &PTE_addr);
public:
- MultiLevelPageTable(const std::string &__name, uint64_t _pid, System
*_sys);
+ MultiLevelPageTable(const std::string &__name, uint64_t _pid,
+ System *_sys);
~MultiLevelPageTable();
void initState(ThreadContext* tc);
diff -r 9f456b5cc474 -r 1e3b3c7a0cba src/mem/multi_level_page_table_impl.hh
--- a/src/mem/multi_level_page_table_impl.hh Sun Nov 23 18:01:08 2014 -0800
+++ b/src/mem/multi_level_page_table_impl.hh Sun Nov 23 18:01:09 2014 -0800
@@ -49,7 +49,8 @@
using namespace TheISA;
template <class ISAOps>
-MultiLevelPageTable<ISAOps>::MultiLevelPageTable(const std::string &__name,
uint64_t _pid, System *_sys)
+MultiLevelPageTable<ISAOps>::MultiLevelPageTable(const std::string &__name,
+ uint64_t _pid, System *_sys)
: PageTableBase(__name, _pid), system(_sys),
logLevelSize(PageTableLayout),
numLevels(logLevelSize.size())
@@ -109,7 +110,8 @@
assert(log_req_size >= PageShift);
uint64_t npages = 1 << (log_req_size - PageShift);
- DPRINTF(MMU, "Allocating %d pages needed for entry in level %d\n",
npages, i-1);
+ DPRINTF(MMU, "Allocating %d pages needed for entry in level %d\n",
+ npages, i - 1);
/* allocate new entry */
Addr next_entry_paddr = system->allocPhysPages(npages);
@@ -121,7 +123,8 @@
p.write<PageTableEntry>(entry_addr, entry);
}
- DPRINTF(MMU, "Level %d base: %d offset: %d entry: %d\n", i,
level_base, offsets[i], next_entry_pnum);
+ DPRINTF(MMU, "Level %d base: %d offset: %d entry: %d\n",
+ i, level_base, offsets[i], next_entry_pnum);
level_base = next_entry_pnum;
}
@@ -133,7 +136,8 @@
template <class ISAOps>
void
-MultiLevelPageTable<ISAOps>::map(Addr vaddr, Addr paddr, int64_t size, bool
clobber)
+MultiLevelPageTable<ISAOps>::map(Addr vaddr, Addr paddr,
+ int64_t size, bool clobber)
{
// starting address must be page aligned
assert(pageOffset(vaddr) == 0);
@@ -153,7 +157,7 @@
p.write<PageTableEntry>(PTE_addr, PTE);
DPRINTF(MMU, "New mapping: %#x-%#x\n", vaddr, paddr);
} else {
- fatal("address 0x%x already mapped to %x", vaddr, entry_paddr);
+ fatal("addr 0x%x already mapped to %x", vaddr, entry_paddr);
}
eraseCacheEntry(vaddr);
@@ -175,7 +179,9 @@
PortProxy &p = system->physProxy;
- for (; size > 0; size -= pageSize, vaddr += pageSize, new_vaddr +=
pageSize) {
+ for (; size > 0;
+ size -= pageSize, vaddr += pageSize, new_vaddr += pageSize)
+ {
Addr PTE_addr;
if (walk(vaddr, false, PTE_addr)) {
PageTableEntry PTE = p.read<PageTableEntry>(PTE_addr);
@@ -306,7 +312,8 @@
template <class ISAOps>
void
-MultiLevelPageTable<ISAOps>::unserialize(Checkpoint *cp, const std::string
§ion)
+MultiLevelPageTable<ISAOps>::unserialize(Checkpoint *cp,
+ const std::string §ion)
{
paramIn(cp, section, "ptable.pointer", basePtr);
}
diff -r 9f456b5cc474 -r 1e3b3c7a0cba src/mem/page_table.cc
--- a/src/mem/page_table.cc Sun Nov 23 18:01:08 2014 -0800
+++ b/src/mem/page_table.cc Sun Nov 23 18:01:09 2014 -0800
@@ -51,7 +51,8 @@
using namespace std;
using namespace TheISA;
-FuncPageTable::FuncPageTable(const std::string &__name, uint64_t _pid, Addr
_pageSize)
+FuncPageTable::FuncPageTable(const std::string &__name,
+ uint64_t _pid, Addr _pageSize)
: PageTableBase(__name, _pid, _pageSize)
{
}
@@ -71,7 +72,7 @@
for (; size > 0; size -= pageSize, vaddr += pageSize, paddr += pageSize) {
if (!clobber && (pTable.find(vaddr) != pTable.end())) {
// already mapped
- fatal("FuncPageTable::allocate: address 0x%x already mapped",
vaddr);
+ fatal("FuncPageTable::allocate: addr 0x%x already mapped", vaddr);
}
pTable[vaddr] = TheISA::TlbEntry(pid, vaddr, paddr);
@@ -89,7 +90,9 @@
DPRINTF(MMU, "moving pages from vaddr %08p to %08p, size = %d\n", vaddr,
new_vaddr, size);
- for (; size > 0; size -= pageSize, vaddr += pageSize, new_vaddr +=
pageSize) {
+ for (; size > 0;
+ size -= pageSize, vaddr += pageSize, new_vaddr += pageSize)
+ {
assert(pTable.find(vaddr) != pTable.end());
pTable[new_vaddr] = pTable[vaddr];
diff -r 9f456b5cc474 -r 1e3b3c7a0cba src/mem/page_table.hh
--- a/src/mem/page_table.hh Sun Nov 23 18:01:08 2014 -0800
+++ b/src/mem/page_table.hh Sun Nov 23 18:01:09 2014 -0800
@@ -93,7 +93,8 @@
Addr pageAlign(Addr a) { return (a & ~offsetMask); }
Addr pageOffset(Addr a) { return (a & offsetMask); }
- virtual void map(Addr vaddr, Addr paddr, int64_t size, bool clobber =
false) = 0;
+ virtual void map(Addr vaddr, Addr paddr, int64_t size,
+ bool clobber = false) = 0;
virtual void remap(Addr vaddr, int64_t size, Addr new_vaddr) = 0;
virtual void unmap(Addr vaddr, int64_t size) = 0;
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