changeset c1ad57c53a36 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c1ad57c53a36
description:
kvm, x86: Adding support for SE mode execution
This patch adds methods in KvmCPU model to handle KVM exits caused by
syscall
instructions and page faults. These types of exits will be encountered
if
KvmCPU is run in SE mode.
diffstat:
src/arch/SConscript | 1 +
src/arch/alpha/pseudo_inst.hh | 45 ++++++++++++++++++++++++++
src/arch/arm/pseudo_inst.hh | 45 ++++++++++++++++++++++++++
src/arch/generic/SConscript | 1 +
src/arch/generic/pseudo_inst.cc | 48 ++++++++++++++++++++++++++++
src/arch/generic/pseudo_inst.hh | 55 ++++++++++++++++++++++++++++++++
src/arch/mips/pseudo_inst.hh | 45 ++++++++++++++++++++++++++
src/arch/power/pseudo_inst.hh | 45 ++++++++++++++++++++++++++
src/arch/sparc/pseudo_inst.hh | 45 ++++++++++++++++++++++++++
src/arch/x86/SConscript | 1 +
src/arch/x86/pseudo_inst.cc | 69 +++++++++++++++++++++++++++++++++++++++++
src/arch/x86/pseudo_inst.hh | 41 ++++++++++++++++++++++++
src/arch/x86/tlb.cc | 20 ++++++-----
src/arch/x86/utility.cc | 4 +-
src/cpu/kvm/base.cc | 13 +++++-
src/sim/pseudo_inst.cc | 11 ++++++
src/sim/system.cc | 10 +++++
util/m5/m5ops.h | 7 ++-
18 files changed, 489 insertions(+), 17 deletions(-)
diffs (truncated from 669 to 300 lines):
diff -r 41ebfed1dc89 -r c1ad57c53a36 src/arch/SConscript
--- a/src/arch/SConscript Sun Nov 23 18:01:08 2014 -0800
+++ b/src/arch/SConscript Sun Nov 23 18:01:08 2014 -0800
@@ -55,6 +55,7 @@
mmapped_ipr.hh
mt.hh
process.hh
+ pseudo_inst.hh
registers.hh
remote_gdb.hh
stacktrace.hh
diff -r 41ebfed1dc89 -r c1ad57c53a36 src/arch/alpha/pseudo_inst.hh
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/alpha/pseudo_inst.hh Sun Nov 23 18:01:08 2014 -0800
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Alexandru Dutu
+ */
+
+#ifndef __ARCH_ALPHA_PSEUDO_INST_HH__
+#define __ARCH_ALPHA_PSEUDO_INST_HH__
+
+#include "arch/generic/pseudo_inst.hh"
+#include "base/misc.hh"
+
+class ThreadContext;
+
+namespace AlphaISA {
+ using GenericISA::m5Syscall;
+ using GenericISA::m5PageFault;
+}
+
+#endif // __ARCH_ALPHA_PSEUDO_INST_HH__
+
diff -r 41ebfed1dc89 -r c1ad57c53a36 src/arch/arm/pseudo_inst.hh
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/arm/pseudo_inst.hh Sun Nov 23 18:01:08 2014 -0800
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Alexandru Dutu
+ */
+
+#ifndef __ARCH_ARM_PSEUDO_INST_HH__
+#define __ARCH_ARM_PSEUDO_INST_HH__
+
+#include "arch/generic/pseudo_inst.hh"
+#include "base/misc.hh"
+
+class ThreadContext;
+
+namespace ArmISA {
+ using GenericISA::m5Syscall;
+ using GenericISA::m5PageFault;
+}
+
+#endif // __ARCH_ARM_PSEUDO_INST_HH__
+
diff -r 41ebfed1dc89 -r c1ad57c53a36 src/arch/generic/SConscript
--- a/src/arch/generic/SConscript Sun Nov 23 18:01:08 2014 -0800
+++ b/src/arch/generic/SConscript Sun Nov 23 18:01:08 2014 -0800
@@ -33,3 +33,4 @@
Source('decode_cache.cc')
Source('mmapped_ipr.cc')
+Source('pseudo_inst.cc')
diff -r 41ebfed1dc89 -r c1ad57c53a36 src/arch/generic/pseudo_inst.cc
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/generic/pseudo_inst.cc Sun Nov 23 18:01:08 2014 -0800
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Alexandru Dutu
+ */
+
+#include "arch/generic/pseudo_inst.hh"
+#include "base/misc.hh"
+
+class ThreadContext;
+
+using namespace GenericISA;
+
+void
+GenericISA::m5Syscall(ThreadContext *tc)
+{
+ panic("m5Syscall not implemented for current ISA");
+}
+
+void
+GenericISA::m5PageFault(ThreadContext *tc)
+{
+ panic("m5PageFault not implemented for current ISA");
+}
diff -r 41ebfed1dc89 -r c1ad57c53a36 src/arch/generic/pseudo_inst.hh
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/generic/pseudo_inst.hh Sun Nov 23 18:01:08 2014 -0800
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Alexandru Dutu
+ */
+
+#ifndef __ARCH_GENERIC_PSEUDO_INST_HH__
+#define __ARCH_GENERIC_PSEUDO_INST_HH__
+
+class ThreadContext;
+
+namespace GenericISA {
+
+/*
+ * This function is executed when the simulation is executing the syscall
+ * handler in System Emulation mode.
+ */
+void
+m5Syscall(ThreadContext *tc);
+
+/*
+ * This function is executed when the simulation is executing the pagefault
+ * handler in System Emulation mode.
+ */
+void
+m5PageFault(ThreadContext *tc);
+
+} // namespace GenericISA
+
+#endif // __ARCH_GENERIC_PSEUDO_INST_HH__
+
diff -r 41ebfed1dc89 -r c1ad57c53a36 src/arch/mips/pseudo_inst.hh
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/mips/pseudo_inst.hh Sun Nov 23 18:01:08 2014 -0800
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Alexandru Dutu
+ */
+
+#ifndef __ARCH_MIPS_PSEUDO_INST_HH__
+#define __ARCH_MIPS_PSEUDO_INST_HH__
+
+#include "arch/generic/pseudo_inst.hh"
+#include "base/misc.hh"
+
+class ThreadContext;
+
+namespace MipsISA {
+ using GenericISA::m5Syscall;
+ using GenericISA::m5PageFault;
+}
+
+#endif // __ARCH_MIPS_PSEUDO_INST_HH__
+
diff -r 41ebfed1dc89 -r c1ad57c53a36 src/arch/power/pseudo_inst.hh
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/power/pseudo_inst.hh Sun Nov 23 18:01:08 2014 -0800
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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