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Ship it! Fine with me, assuming that our implementations of those features are indeed complete. - Steve Reinhardt On Dec. 22, 2014, 4:38 p.m., Gabe Black wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2591/ > ----------------------------------------------------------- > > (Updated Dec. 22, 2014, 4:38 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10608:fc26fb9c80b9 > --------------------------- > x86: Enable three bits in the FamilyModelStepping ECX CPUID bitfield. > > These are for the monitor/mwait instructions, SSSE3, and XSAVE. > > > Diffs > ----- > > src/arch/x86/cpuid.cc a0cb57e1c072965dcdd51465beff37b264b41424 > > Diff: http://reviews.gem5.org/r/2591/diff/ > > > Testing > ------- > > > Thanks, > > Gabe Black > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
