> On Dec. 23, 2014, 5:19 a.m., Steve Reinhardt wrote: > > Fine with me, assuming that our implementations of those features are > > indeed complete.
They aren't, but I think the bits that are missing will trigger warnings. - Gabe ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2591/#review5706 ----------------------------------------------------------- On Dec. 23, 2014, 12:38 a.m., Gabe Black wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2591/ > ----------------------------------------------------------- > > (Updated Dec. 23, 2014, 12:38 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10608:fc26fb9c80b9 > --------------------------- > x86: Enable three bits in the FamilyModelStepping ECX CPUID bitfield. > > These are for the monitor/mwait instructions, SSSE3, and XSAVE. > > > Diffs > ----- > > src/arch/x86/cpuid.cc a0cb57e1c072965dcdd51465beff37b264b41424 > > Diff: http://reviews.gem5.org/r/2591/diff/ > > > Testing > ------- > > > Thanks, > > Gabe Black > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
