> On Jan. 26, 2015, 8:33 p.m., Andreas Hansson wrote: > > Please rather make sure that responses are sunk before generating requests > > (i.e. do not call sendTimingReq as part of recvTimingResp). That is what I > > did for the X86 table walker. Would that be ok? > > Jason Power wrote: > I'll definitely try to do that in my code, but the problem is in > TimingSimpleCPU. I found this problem if I hook TimingSimpleCPU directly to > the crossbar (i.e. without an L1 I/D cache). I know this isn't a very common > configuration, but it seems like something the crossbar should support. > > I'm not an expert in how the TimingSimpleCPU code works, and from a > cursory look I don't understand exactly where the request/response logic is. > This problem definitely occurs in the instruction fetch logic, and maybe in > the data fetch logic as well. > > Here's a link to the config file I'm using: > http://pages.cs.wisc.edu/~david/courses/cs752/Spring2015/gem5-tutorial/_downloads/simple.py > (it should be available outside of Wisconsin). This config file works before > revision 10656, but rev 10656 breaks it. > > I don't really have time right now to dig into the TimingSimpleCPU code, > so I'm going to have the class use gem5-stable. Going forward, do we want to > fix TimingSimpleCPU, or is there something else we should do?
I can have a look, it shouldn't be too complicated. I'd say let's just fix the timing cpu. - Andreas ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2617/#review5788 ----------------------------------------------------------- On Jan. 26, 2015, 8:28 p.m., Jason Power wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2617/ > ----------------------------------------------------------- > > (Updated Jan. 26, 2015, 8:28 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10667:b87ca279e34d > --------------------------- > mem: Fix race condition in crossbar routing table > > The routing table in the corssbar needs to be updated before the > request response is sent. Otherwise, the requestor may delete the > current request and allocate a new one, causing an address alias > in the routing table. > > > Diffs > ----- > > src/mem/coherent_xbar.cc bd376adfb7d4 > > Diff: http://reviews.gem5.org/r/2617/diff/ > > > Testing > ------- > > > Thanks, > > Jason Power > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
