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Review request for Default. Repository: gem5 Description ------- Changeset 10720:bd4fc2b06322 --------------------------- mem: Downstream components consumes new crossbar delays This patch makes the caches and memory controllers consume the delay that is annotated to a packet by the crossbar. Previously many components simply threw these delays away. Note that the devices still do not pay for these delays. Diffs ----- src/mem/cache/cache_impl.hh c6cb94a14fea src/mem/dram_ctrl.cc c6cb94a14fea src/mem/dramsim2.cc c6cb94a14fea Diff: http://reviews.gem5.org/r/2662/diff/ Testing ------- Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
